Parallel processing system with processor array having SIMD/MIMD instruction processing

• US 4,891,787 A
• Filed: 12/17/1986
• Issued: 01/02/1990
• Est. Priority Date: 12/17/1986
• Status: Expired due to Term

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Gifford, David K.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/943,376
• Time in Patent Office: 1,112 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/205
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruciton. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.

Claims

1. A control mechanism for generating instructions to be used in operating a digital data processing system including a plurality of processing means operating in parallel to execute a conditional statement to perform one of a plurality of conditional responses in response to the value of a conditional proposition, each instruction belonging to one of two classes and each of said processing means including an enabling flag for controlling the operation of said processing means in response to the class of each instruction, said control mechanism comprising:

A. conditional response instruction generating means for compiling instructions for each of said conditional responses and enabling said instructions for each conditional response to be stored in a separate instruction list;

B. transmission instruction generating means responsive to the generation by said conditional response instruction generating means of the instruction lists for generating instructions processed by said processing means regardless of the condition of said enabling flag for storing the consequent list and the alternative list;

D. proposition instruction generating means for compiling proposition instructions to be executed by all of the processing means, said processing means conditioning their enabling means in response thereto;

E. condition instruction generating means for generating instructions for iteratively enabling said processing means to execute instructions from their conditional response instruction lists if their enabling flags have a selected condition, and instructions executed by all processing means to enable them to adjust the condition of their enabling flags between execution of instructions from the respective lists.

2. A control mechanism as defined in claim 1 wherein said conditional responses include a consequent response and an alternative response, said conditional response instruction generating means including:

A. consequent instruction generating means for compiling instructions for the consequent and enabling said instructions to be stored in a consequent list; and

B. alternative instruction generating means for compiling instructions for the alternative and enabling said instructions to be stored in an alternative list.

3. A control mechanism as defined in claim 2 wherein said condition instruction generating means includes:

A. consequent instruction enabling means for generating instructions for enabling said processing means to execute instructions from its consequent list in response to the condition of its enabling flag;

B. enabling flag instruction generating means for generating instructions to enable all of said processing means to complement their enabling flags regardless of the condition of their enabling flags, and

C. alternative instruction enabling means for generating instructions for enabling said processing means to execute instructions from its alternative list in response to the condition of its enabling flag.

4. A control mechanism as defined in claim 1 wherein each of said processing means further includes MIMD flag means, said condition instruction generating means including means for generating MIMD flag conditioning intructions to be executed by said processing means to establish said MIMD flag to a selected condition at the beginning of execution of instructions generated by said condition instruction generating means and MIMD flag complement instructions to complement the condition of said MIMD flag at the end of execution of instructions generated by said condition instruction generating means.