Three port random access memory
First Claim
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1. Solid state memory device capable of receiving and transmitting data in a serial format and permitting random access to the data, characterized by:
- (a) a random access memory array containing a plurality of data bits;
(b) a plurality of serial access memories;
(c) transfer circuitry including a plurality of transfer gates communicating with the random access memory array, the transfer circuitry communicating between the transfer gates and the serial access memories in order to transfer data between the random access memory and the serial access memories;
(d) the transfer circuitry transferring said data selectively to any one of said plurality of serial access memories;
(e) the transfer circuitry including a transfer control circuit controlling with which serial access memory said transfer of data is performed; and
(f) a serial address connection for at least two of the serial access memories.
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Abstract
A three port memory device has two serial ports and a random access memory port. The random access memory port is addressed to a random access memory in a conventional manner, using RAS and CAS address signals. Data may also be supplied and retrieved through two serial ports to a pair of serial access memories for transfer between the serial ports and the random access memory. This configuration permits formatted data to be simultaneously assessed through the two serial ports, while the random access memory port is being accessed.
57 Citations
20 Claims
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1. Solid state memory device capable of receiving and transmitting data in a serial format and permitting random access to the data, characterized by:
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(a) a random access memory array containing a plurality of data bits; (b) a plurality of serial access memories; (c) transfer circuitry including a plurality of transfer gates communicating with the random access memory array, the transfer circuitry communicating between the transfer gates and the serial access memories in order to transfer data between the random access memory and the serial access memories; (d) the transfer circuitry transferring said data selectively to any one of said plurality of serial access memories; (e) the transfer circuitry including a transfer control circuit controlling with which serial access memory said transfer of data is performed; and (f) a serial address connection for at least two of the serial access memories. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. Solid state memory device capable of receiving and transmitting data in a serial format and permitting random access to the data, characterized by:
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(a) a random access memory array containing a plurality of data bits, (b) a plurality of serial access memories; (c) the random access memory array being addressable by external read commands and by external write commands; (d) the serial address memories being static memory circuits which are each addressed in at least one static sequence; (e) a plurality of transfer gates communicating with the random access memory array and the serial access memories in order to transfer data between the random access memory and one of the serial access memories; (f) the plurality of transfer gates transferring said data selectively to any one of said plurality of serial access memories; and (g) a serial address connection for at least two of the serial access memories. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification