Complementary current mirror for correcting input offset voltage of diamond follower, especially as input stage for wide-band amplifier

• US 4,893,091 A
• Filed: 10/11/1988
• Issued: 01/09/1990
• Est. Priority Date: 10/11/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Inventors: Wang, Anthony D., Lillis, William J.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/255,774
• Time in Patent Office: 455 Days
• Field of Search: 330/261, 330/267, 330/268, 330/288, 330/299, 330/253, 330/264, 330/269, 330/277, 323/315, 323/316
• US Class Current: 330/253
• CPC Class Codes: H03F 1/307 in push-pull amplifiers
• CPC Class Codes: H03F 3/3001 with field-effect transistors
• CPC Class Codes: H03F 3/3076 with symmetrical driving of the end stage

Abstract

A complementary current mirror includes a PNP transistor and an NPN transistor, one of which serves as a control transistor and the other of which serves as an output transistor. A V_BE voltage generated by forcing a control current into or out of the emitter of the control transistor is imposed between the base and emitter of the output transistor to produce a controlled current in the collector of the output transistor. A first such current mirror, with an NPN control transistor, and a second such current mirror, with a PNP control transistor, are driven by the same control current to supply first and second input bias currents to a diamond follower circuit in the same integrated circuit as the first and second current mirror circuits to face the V_BE voltage of the PNP and NPN transistors of the diamond follower circuit to be equal despite variation in saturation currents of the PNP and NPN transistsors. This results in zero input offset for the diamond follower circuit.

Claims

1. A method for producing zero offset voltage in a diamond follower circuit including first and second bias input terminals, an input terminal and an output terminal, the method comprising the steps of:

(a) producing a first NPN V_BE voltage;

(b) imposing the first NPN V_BE voltage between a base and an emitter of a first PNP transistor to produce a first bias current;

(c) using the first bias current to equalize V_BE voltages of a first pair of opposite conductivity type transistors one transistor of the first pair having a base coupled to the input terminal and an emitter coupled to the first bias input terminal, another transistor of the first pair having an emitter coupled to the output terminal and a base coupled to the first bias input terminal;

(d) producing a first PNP V_BE voltage;

(e) imposing the first PNP V_BE voltage between a base and an emitter of a first NPN transistor to produce a second bias current;

(f) using the second bias current to equalize V_BE voltages of a second pair of opposite conductivity type transistors, one transistor of the second pair having a base coupled to the input terminal and an emitter coupled to the second bias input terminal, another transistor of the second pair having an emitter coupled to the output terminal and a base coupled to the second bias input terminal, whereby the voltage between the input terminal and the output terminal is zero.

2. The method of claim 1 including causing a control current to flow through a second NPN transistor and a second PNP transistor, respectively.

3. The method of claim 2 wherein the first pair of opposite conductivity transistors includes a third PNP transistor and a third NPN transistor, and wherein step (c) includes causing the first bias current to flow through the third PNP transistor to produce a second PNP V_BE voltage, and wherein the second pair of opposite conductivity transistors includes a fourth NPN transistor and a fourth PNP transistor, and wherein step (f) includes causing the second bias current to flow through the fourth NPN transistor to produce a second NPN V_BE voltage, and imposing the sum of the second PNP V_BE voltage and the second NPN V_BE voltage between the base of the third NPN transistor and the base of the fourth PNP transistor.

4. A zero offset amplifier, comprising in combination:

(a) first and second differential input terminals;

(b) first and second bias input terminals;

(c) first and second differential output terminals;

(d) a PNP first transistor having an emitter coupled to the first bias input terminal, a collector coupled to a first supply voltage conductor, and a base coupled to the first differential input terminal;

(e) an NPN second transistor having an emitter coupled to the second bias input terminal, a collector coupled to a second supply voltage conductor, and a base coupled to the first differential input terminal;

(f) an NPN third transistor having a base coupled to the first bias input terminal, an emitter coupled to the second differential input terminal, and a collector coupled to the first differential output terminal;

(g) a PNP fourth transistor having a base coupled to the second bias input terminal, an emitter coupled to the second differential input terminal, and a collector coupled to the second differential output terminal;

(h) a bias current control circuit having a bias current sink terminal and a bias current source terminal;

(i) a first complementary current mirror including

i. an NPN fifth transistor having a collector and base coupled to the second supply voltage conductor and an emitter coupled to the bias current sink terminal,

ii. a PNP sixth transistor having an emitter coupled to the second supply voltage conductor, a base coupled to the bias current sink terminal, and a collector coupled to the first bias input terminal, the NPN fifth transistor and the PNP sixth transistor coacting to produce a first bias current that compensates the PNP first transistor for any difference in the normalized saturation currents of the PNP first transistor and the NPN third transistor;

(j) a second complementary current mirror including

i. a PNP seventh transistor having a base and collector coupled to the first supply voltage conductor and an emitter coupled to the bias source terminal,

ii. an NPN eighth transistor having an emitter coupled to the first supply voltage conductor, a base coupled to the bias current source terminal, and a collector coupled to the second bias input terminal, the PNP seventh transistor and the NPN eighth transistor coacting to produce a second bias current that compensates the NPN second transistor for any difference in the normalized saturation currents of the NPN second transistor and the PNP fourth transistor.

5. The zero offset amplifier of claim 4 including a first load device coupled between the first differential output terminal and the second supply voltage conductor, and a second load device coupled between the second differential output terminal and the first supply voltage conductor.

6. The zero offset amplifier of claim 5 wherein the PNP first transistor has a normalized saturation current which is substantially different than that of the NPN second transistor.

7. The zero offset amplifier of claim 5 wherein the first load device is a first resistor and the second load device is a second resistor.

8. A method of producing a current which represents an inequality between a parameter of a first PNP transistor and a first NPN transistor, comprising the steps of:

(a) forcing a control current through the first PNP transistor to generate a first V_BE voltage;

(b) applying the first V_BE voltage between the base and emitter of the first NPN transistor to cause a controlled current to flow in the first NPN transistor, the controlled current including a first component which is proportional to the control current and a second component which is related to the inequality, wherein the inequality is represented by a ratio of the normalized saturation currents of the first PNP transistor and the first NPN transistor, respectively;

(c) forcing the controlled current through a second NPN transistor which has the same normalized saturation current as the first NPN transistor to produce a second V_BE voltage which is compensated for the difference between the normalized saturation currents of the first PNP transistor and the first NPN transistor and applying the second V_BE voltage between the base and emitter of a second PNP transistor which has the same normalized saturation current as the first PNP transistor to produce a current in the second PNP transistor which is substantially unaffected by the difference between the normalized saturation currents.

9. A method of producing a current which represents an inequality between a parameter of a first NPN transistor and a first PNP transistor, comprising the steps of:

(a) forcing a control current through the first NPN transistor to generate a first V_BE voltage;

(b) applying the first V_BE voltage between the base and emitter of the first PNP transistor to cause a controlled current to flow in the first PNP transistor, the controlled current including a first component which is proportional to the control current and a second component which is related to the inequality, wherein the inequality is represented by a ratio of the normalized saturation currents of the first NPN transistor and the first PNP transistor, respectively;

(c) forcing the controlled current through a second PNP transistor which has the same normalized saturation current as the first PNP transistor to produce a second V_BE voltage which is compensated for the difference between the normalized saturation currents of the first PNP transistor and the first NPN transistor and applying the second V_BE voltage between the base and emitter of a second NPN transistor which has the same normalized saturation current as the first NPN transistor to produce a current in the second NPN transistor which is substantially unaffected by the difference between the normalized saturation currents.

10. A method of producing a current which represents an inequality between a parameter of a first MOSFET of a first channel type and a second MOSFET of a second channel type, comprising the steps of:

(a) forcing a control current through a source electrode of the first MOSFET to generate a first gate-to-source voltage;

(b) applying the first gate-to-source voltage between gate electrode and a source electrode of the second MOSFET to cause a controlled current to flow in the second MOSFET, the controlled current including a first component which is proportional to the control current and a second component which is related to the inequality.

11. A method of adjusting an offset voltage of a diamond follower circuit including first and second bias input terminals, first and second differential input terminals and first and second differential output terminals, a PNP first transistor having an emitter coupled to the first bias input terminal, a collector coupled to a first supply voltage conductor, and a base coupled to the first differential input terminal, an NPN second transistor having an emitter coupled to the second bias input terminal, a collector coupled to a second supply voltage conductor, and a base coupled to the first differential input terminal, an NPN third transistor having a base coupled to the first bias input terminal, an emitter coupled to the second differential input terminal, and a collector coupled to the first differential output terminal, a PNP fourth transistor having a base coupled to the second bias input terminal, an emitter coupled to the second differential input terminal, and a collector coupled to the second differential output terminal, the method comprising the steps of:

(a) supplying a first bias current to the first bias input terminal;

(b) sinking a second bias current from the second bias input terminal;

(c) adjusting the first bias current to equalize a V_BE voltage of the PNP first transistor and the NPN third transistor, and adjusting the second bias current to equalize a V_BE voltage of the NPN second transistor and the PNP fourth transistor.

12. A method for producing zero offset voltage in a diamond follower circuit including first and second bias input terminals, an input terminal and an output terminal, the method comprising the steps of:

(a) producing a first N channel MOSFET V_GS voltage;

(b) imposing the first N channel MOSFET V_GS voltage between a gate and an source of a first P channel MOSFET to produce a first bias current;

(c) using the first bias current to equalize V_GS voltages of a first pair of opposite conductivity type MOSFETs, one MOSFET of the first pair having a gate coupled to the input terminal and a source coupled to the first bias input terminal, another MOSFET of the first pair having an source coupled to the output terminal and a gate coupled to the first bias input terminal;

(d) producing a first P channel MOSFET V_GS voltage;

(e) imposing the first P channel MOSFET V_GS voltage between a gate and a source of a first N channel MOSFET to produce a second bias current;

(f) using the second bias current to equalize V_GS voltages of a second pair of opposite conductivity type MOSFETs, one MOSFET of the second pair having a gate coupled to the input terminal and a source coupled to the second bias input terminal, another MOSFET of the second pair having a source coupled to the output terminal and a gate coupled to the second bias input terminal, whereby the voltage between the input terminal and the output terminal is zero.

13. A zero offset amplifier, comprising in combination:

(a) first and second differential input terminals;

(b) first and second bias input terminals;

(c) first and second differential output terminals;

(d) a P channel first MOSFET having a source coupled to the first bias input terminal, a drain coupled to a first supply voltage conductor, and a gate coupled to the first differential input terminal;

(e) an N channel second MOSFET having a source coupled to the second bias input terminal, a drain coupled to a second supply voltage conductor, and a gate coupled to the first differential input terminal;

(f) an N channel third MOSFET having a gate coupled to the first bias input terminal, a source coupled to the second differential input terminal, and a drain coupled to the first differential output terminal;

(g) a P channel fourth MOSFET having a gate coupled to the second bias input terminal, a source coupled to the second differential input terminal, and a drain coupled to the second differential output terminal;

(h) a bias current control circuit having a bias current sink terminal and a bias current source terminal;

(i) a first complementary current mirror including

i. a N channel fifth MOSFET having a drain and gate coupled to the second supply voltage conductor and a source coupled to the bias current sink terminal,

ii. a P channel sixth MOSFET having a source coupled to the second supply voltage conductor, a gate coupled to the bias current sink terminal, and a drain coupled to the first bias input terminal, the N channel fifth MOSFET and the P channel sixth MOSFET coacting to produce a first bias current that compensates the P channel first MOSFET for any difference in the normalized saturation currents of the P channel first MOSFET and the N channel third MOSFET;

(j) a second complementary current mirror including

i. a P channel seventh MOSFET having a gate and drain coupled to the first supply voltage conductor and a source coupled to the bias current source terminal,

ii. an N channel eight MOSFET having a source coupled to the first supply voltage conductor, a gate coupled to the bias current source terminal, and a drain coupled to the second bias input terminal, the P channel seventh MOSFET and the N channel eighth MOSFET coacting to produce a second bias current that compensates the N channel second MOSFET for any difference in the normalized saturation currents of the N channel second MOSFET and the P channel fourth MOSFET.

14. A complementary current mirror, comprising in combination:

(a) an input terminal for conducting a control current;

(b) an output terminal for conducting a controlled current;

(c) a supply voltage conductor;

(d) a control field effect transistor having a source electrode connected to the input terminal and conducting the control current, and a gate electrode and a drain electrode both connected to the supply voltage conductor;

(e) an output field effect transistor having a source electrode connected to the supply voltage conductor, a gate electrode connected to the input terminal, and a drain electrode connected to the output terminal, the output transistor and the input transistor being of opposite conductivity types,

the control field effect transistor and the output field effect transistor coacting to produce the controlled current in the drain electrode of the output field effect transistor so that the controlled current is representative of both the control current and a parametric difference between the control field effect transistor and the output field effect transistor.

15. The complementary current mirror of claim 14 wherein the control transistor is an enhancement mode N channel field effect transistor and the output transistor is an enhancement mode P channel field effect transistor.

16. The complementary current mirror of claim 14 wherein the control transistor is an enhancement mode P channel field effect transistor and the output transistor is an enhancement mode N channel field effect transistor.

17. A method of adjusting an offset voltage of a diamond follower circuit including first and second bias input terminals, first and second differential input terminals and first and second differential output terminals, a P channel first MOSFET having a source coupled to the first bias input terminal, a drain coupled to a first supply voltage conductor, and a gate coupled to the first differential input terminal, an N channel second MOSFET having a source coupled to the second bias input terminal, a drain coupled to a second supply voltage conductor, and a gate coupled to the first differential input terminal, an N channel third MOSFET having a gate coupled to the first bias input terminal, a source coupled to the second differential input terminal, and a drain coupled to the first differential output terminal, a P channel fourth MOSFET having a gate coupled to the second bias input terminal, a source coupled to the second differential input terminal, and a drain coupled to the second differential output terminal, the method comprising the steps of:

(a) supplying a first bias current to the first bias input terminal;

(b) sinking a second bias current from the second bias input terminal;

(c) adjusting the first bias current to equalize a V_GS voltage of the P channel first MOSFET and the N channel third MOSFET, and adjusting the second bias current to equalize a V_GS voltage of the N channel second MOSFET and the P channel fourth MOSFET.