Digital radio frequency receiver
First Claim
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1. An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising:
- means for generating a noise signal which does not have any substantial energy at said given frequency;
means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter;
clock means for generating periodic pulses at a first frequency coupled to said A/D converter causing the latter to make A/D conversions in response to said pulses; and
the resultant signal produced by said summing means containing the signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter.
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Abstract
A digital radio receiver is described. The digital receiver of the present invention contemplates a digital radio receiver which operates on a received analog signal which has been converted to a digital form after preselection at the output of the antenna. The digital receiver of the present invention comprises a preselector, a high-speed analog-to-digital (A/D) converter, a digitally implemented intermediate-frequency (IF) selectivity section having an output signal at substantially baseband frequencies, and digital signal processor (DSP) circuit performing demodulation and audio filtering. The radio architecture of the present invention is programmably adaptable to virtually every known modulation scheme and is particularly suitable for implementation on integrated circuits.
536 Citations
162 Claims
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1. An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising:
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means for generating a noise signal which does not have any substantial energy at said given frequency; means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to said A/D converter causing the latter to make A/D conversions in response to said pulses; and the resultant signal produced by said summing means containing the signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data comprising the steps of:
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generating a noise signal which does not have any substantial energy at said given frequency; summing the analog AC input signal and said noise signal to produce a resultant signal which contains a signal component corresponding to said AC input signal; coupling the resultant signal to the input of the A/D converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses; and the A/D converter converting said signal component into digital data representative of said analog AC input signal, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, wherein converting by the A/D converter of the signal component into digital data effectively extends the threshold sensitivity of the A/D converter. - View Dependent Claims (12, 13, 14, 15, 16)
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17. In a communications receiver having a bandpass filter with a bandwidth which permits the passage of an analog radio frequency (RF) input signal having a frequency within a predetermined range of frequencies and an analog to digital (A/D) converter having a digital data output, the improvement comprising:
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means for generating a noise signal which does not have any substantial energy within said range of frequencies; means for summing said filtered analog RF input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to the A/D converter causing the latter to make A/D conversions in response thereto; said summing means producing a resultant signal containing a signal component corresponding to said analog RF input signal which is converted by the A/D converter into a digital data representation, said A/D converter having a given threshold sensitivity and the magnitude of said AC input signal being less than said threshold sensitivity, said signal component corresponding to the AC input signal being converted by the A/D into digital data, whereby AC input signals having a magnitude less than said given threshold sensitivity of the A/D converter can be converted into digital data thereby extending the threshold sensitivity of the A/D converter. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method for converting an analog radio frequency (RF) signal having a given frequency into digital data comprising the steps of:
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bandpass filtering said analog RF signal; storing a first signal corresponding to an instantaneous magnitude of said filtered analog RF signal; generating a noise signal which does not have any substantial energy at said given frequency; summing said first signal and said noise signal to produce a resultant signal; coupling said resultant signal to an analog to digital (A/D) converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, said A/D converter having a given threshold sensitivity and the magnitude of said RF signal being less than said threshold sensitivity, wherein the converting by the A/D converter of the signal component into digital data effectively extends the threshold sensitivity of the A/D converter. - View Dependent Claims (28, 29, 30, 31, 32)
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33. An apparatus for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data, comprising:
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means for generating a noise signal which does not have any substantial energy at said given frequency; means for summing said analog AC input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to said AD converter causing the latter to make A/D conversions in response to said pulses, the ratio of the rate of said periodic pulses to the bandwidth of said analog AC input signal being greater than 10; and the resultant signal produced by said summing means containing a signal component corresponding to said analog AC input signal which is converted by the A/D converter into a digital data representation. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A method for extending the threshold sensitivity of an analog to digital (A/D) converter that converts an analog alternating current (AC) input signal having a given frequency into digital data comprising the steps of:
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generating a noise signal which does not have any substantial energy at said given frequency; summing the analog AC input signal and said noise signal to produce a resultant signal which contains a signal component corresponding to said AC input signal; coupling the resultant signal to the input of the A/D converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, the ratio of the rate of the clock pulses to the bandwidth of the analog AC input signal being greater than 10; and the A/D converter converting said signal component into digital data representative of said analog AC input signal. - View Dependent Claims (43, 44, 45, 46)
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47. In a communications receiver having a bandpass filter with a bandwidth which permits the passage of an analog radio frequency (RF) input signal having a frequency within a predetermined range of frequencies and an analog to digital (A/D) converter having a digital data output, the improvement comprising:
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means for generating a noise signal which does not have any substantial energy within said range of frequencies; means for summing said filtered analog RF input signal and said noise signal to produce a resultant signal that is coupled to an input of the A/D converter; clock means for generating periodic pulses at a first frequency coupled to the A/D converter causing the latter to make A/D conversions in response thereto, the ratio of the rate of said periodic pulses to the bandwidth of said analog AC input signal being greater than 10; and said summing means producing a resultant signal containing a signal component corresponding to said analog RF input signal which is converted by the A/D converter into a digital data representation. - View Dependent Claims (48, 49, 50, 51, 52, 53, 54, 55)
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56. A method for converting an analog radio frequency (RF) signal having a given frequency into digital data comprising the steps of:
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bandpass filtering said analog RF signal; storing a first signal corresponding to an instantaneous magnitude of said filtered analog RF signal; generating a noise signal which does not have any substantial energy at said given frequency; summing said first signal and said noise signal to produce a resultant signal; coupling said resultant signal to an analog to digital (A/D) converter; generating periodic clock pulses at a first frequency which are coupled to said A/D converter and cause A/D conversions to be made in response to said pulses, the ratio of the rate of the clock pulses to the bandwidth of the analog RF signal being greater than 10. - View Dependent Claims (57, 58, 59, 60)
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61. A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device, comprising, in combination:
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clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz; and first and second digital filtering means, each comprising; a decomposed, internally multiplexed, filter section coupled to said digitized output signals; sample rate reducing means coupled to said decomposed filter section; a multiplierless digital filter section coupled to said sample rate reducing means; whereby, said first and second digital filtering means operate to selectively band-limit the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals. - View Dependent Claims (62, 63, 64, 67, 68, 69, 70, 71)
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65. A digital zero-IF selectivity section for operating on a received input signal in a receiver, comprising, in combination;
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clock means for providing at least a first and second periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized signals for providing first and second digitized output signals such that said first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz; first and second digital filtering means, each of said first and second digital filtering means comprising at least one digital filtering section coupled to a sample rate reducing means, and each of said first and second digital filtering means being coupled to said clock means for providing first and second filtered digitized output signals; multiplexing means coupled to said first and second digital filter means to provide a multiplex output signal; third digital filtering means, coupled to said multiplex means, comprising at least one digital filtering section, coupled to said clock means, for providing a selected order filter and to provide a filtered multiplex signal; demultiplexing means coupled to said clock means and said filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
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66. A digital zero-If selectivity section for operating on a recovered input signal in a receiver, comprising, in combination:
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clock means for providing a periodic first clock signal; means for dividing the frequency of said clock signal to provide a second clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized output signals such that said first and second digitized output signals occupy a selected frequency band centered substantially at zero Hertz; first and second digital filtering section means respectively coupled to receive said first and second digitized output signals and each of said first and second digital filtering section means being coupled to said clock means for providing first and second filtered digitized output signals; first and second data sampling rate reducer means respectively coupled to said first and second filtered digitized output signals for providing first and second reduced rate data signals; multiplexing means coupled to said first and second reduced rate data signals to provide a multiplex output signal; third digital filtering section means coupled to said second clock signal and said multiplex output signal to provide a first filtered multiplex signal; fourth digital filtering section means coupled to said second clock signal and said first filtered multiplex signal to provide a second filtered multiplex signal; fifth digital filtering section means coupled to said second clock signal and said second filtered multiplex signal to provide a third filtered multiplex signal; and demultiplexing means coupled to said second clock signal and said third filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
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72. A digital zero-IF selectivity section circuit operating on a first and second input signal in a transmitter device, comprising, in combination:
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clock means for providing a periodic clock signal; digital oscillator means, coupled to said clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; first and second digital filtering means, coupled to the first and second input signals and said clock means, for selectively band-limiting the frequency spectrum of said first and second input signals thereby providing first and second filtered input signals; and means for digital quadrature mixing said first and second filtered input signals and said first and second digitized signals to provide first and second digitized output signals. - View Dependent Claims (73, 74, 75, 76, 77, 78, 79, 80, 81, 82)
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83. In a receiver for receiving and periodically presenting a received digital input signal to an intermediate frequency section, the improvement comprising:
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clock means for providing a periodic clock signal; a digital oscillator means, coupled to clock means, for providing first and second digitized discrete-time signals such that said first digitized discrete-time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the digital input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero hertz; and first and second digital filtering means, coupled to said digital quadrature mixing means and to said clock means, for selectively band-limiting the frequency spectrum of said first and second digitized output signals providing first and second filtered digitized output signals, each of said digital filtering means comprising; at least one digital filtering section intercoupled by a sample rate reducing means; multiplexing means coupled to said digital filter sections to provide a multiplex output signal; third digital filtering means, coupled to said multiplex means, comprising at least one digital filtering section for providing a selected order filter and to provide a filtered multiplex signal; demultiplexing means coupled to said clock means and said filtered multiplex signal for providing first and second output signals such that said first and second output signal occupy a frequency band substantially centered at zero Hertz.
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84. A digital zero-IF selectivity section circuit operating on a recovered input signal in a receiver device comprising, in combination:
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clock means for providing a first and second periodic clock signal, such that said second clock signal has a period approximately twice that of said first clock signal; digital oscillator means, coupled to said first clock signal, for providing first and second digitized discrete-time signals, such that said first digitized discrete time signal leads said second digitized discrete time signal by 90 degrees in phase; means for digital quadrature mixing the input signal and said first and second digitized discrete time signals to provide first and second digitized output signals occupying a selected frequency band centered substantially at zero Hertz; and first and second digital filtering means, each comprising; at least two digital filter sections cascaded together for achieving a selected order digital filter, at least the first section comprising; demultiplexing means, coupled to said digitized output signals for demultiplexing same into at least two demultiplexed signals; first filtering means, coupled to said second clock signal, for filtering said demultiplexed signals providing at least two filtered demultiplexed signals; multiplexing means for multiplexing said filtered demultiplexed signals into a multiplexed signal which represents a selectively band-limited portion of said input signal; and second filtering means coupled to said first clock signal and said multiplexed signal for providing a combined and filtered multiplexed output signal; sample rate reducing means, coupled at least between the first and second filter sections, for reducing the operating speed of subsequent filter sections, each of said subsequent filter sections comprising; first binary summing means coupled to an input signal and a second binary delayed signal for providing a first binary sum signal; first binary shifting means coupled to said first binary sum signal for providing a shifted first binary sum signal; second binary summing means coupled to said shifted first sum signal and a first binary delayed signal for providing a second binary sum signal; first binary storage means coupled to said second binary sum signal for providing said first binary delayed signal; third binary summing means coupled to said first binary delayed signal and said second delayed binary signal for providing a third binary sum signal; second binary shifting means coupled to said third binary sum signal for providing a shifted third binary sum signal; fourth binary summing means coupled to said shifted third binary sum signal and said second binary delayed signal for providing a fourth binary sum signal; second binary storage means coupled to said fourth binary sum signal for providing said second binary delayed signal comprising a filtered digitized output signal; whereby, said first and second digital filtering means operate to selectively band-limit the frequency spectrum of said first and second digitized output signals thereby providing first and second filtered digitized output signals.
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85. An apparatus for substantially digitally processing a wideband analog signal containing a desired narrow band analog signal, comprising:
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(a) means, including coupling means and filter means for receiving and filtering a wideband analog signal containing a desired narrowband analog signal; (b) digitizing means, coupled to said filter means, for periodically sampling and converting said wideband analog signal to a sampled wideband digital signal; (c) digital means, coupled to said digitizing means, for selecting the desired sampled narrowband digital signal from the sampled wideband digital signal, wherein said digital means includes a digital quadrature oscillator means, a digital quadrature multiplier/mixer means, a digital quadrature narrowband lowpass filter means, and means for programmably controlling the bandwidth of said digital quadrature lowpass filter means. - View Dependent Claims (86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106)
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107. A method for substantially digitally processing a wideband analog signal containing a desired narrowband analog signal, comprising the steps of:
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(a) receiving and filtering a wideband analog signal containing a desired narrowband analog signal; (b) periodically sampling and converting said wideband analog signal to a sampled wideband digital signal; (c) selecting the desired sampled narrowband digital signal from the sampled wideband digital signal; and (d) programmably controlling the bandwidth of the sampled narrowband digital signal; (e) demodulating said sampled narrowband digital signal. - View Dependent Claims (108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123)
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124. An apparatus for digitally processing a wideband radio frequency (RF) signal containing a desired narrowband signal, comprising:
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(a) means, including antenna means for receiving (RF) signals containing said wideband (RF) signal; (b) filter means, coupled to said antenna means, for filtering said wideband (RF) signal; (c) digitizing means, coupled to said filter means, for periodically sampling and converting said wideband RF signal to a sampled wideband digital signal; (d) digital means, coupled to said digitizing means, for selected the desired sampled narrowband signal from the sampled wideband digital signal; and (e) digital processing means for demodulating said sampled narrowband digital signal wherein said digital processing means further includes means for additional digital filtering and sampling rate reduction. - View Dependent Claims (125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146)
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147. A method for substantially digitally processing a wideband radio frequency (RF) signal containing a desired narrowband signal, comprising the steps of:
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(a) receiving (RF) signals containing said wideband RF signal; (b) filtering said wideband RF signal; (c) periodically sampling and converting said filtered wideband (RF) signal to a sampled wideband digital signal; (c) selecting the desired sampled narrowband digital signal from the sampled wideband digital signal by generating a digital quadrature local oscillator signal, quadrature multiplying the quadrature local oscillator signal by the sampled wideband digital signal to produce a product signal, digital quadrature narrowband lowpass filtering the product signal to produce the sampled narrowband digital signal, and programmably controlling the bandwidth of said sampled narrowband digital signal; (d) digitally demodulating said sampled narrowband digital signal. - View Dependent Claims (148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162)
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Specification
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Current AssigneeMotorola, Inc. (Motorola Solutions, Inc.)
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Original AssigneeMotorola, Inc. (Motorola Solutions, Inc.)
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InventorsLillie, Ross J., Zebrose, Katherine L., Longley, Lester A., Jasper, Steven C., Turney, William J., Janc, Robert V.
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Primary Examiner(s)Griffin, Robert L.
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Assistant Examiner(s)Huseman, Marianne
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Application NumberUS06/890,804Time in Patent Office1,265 DaysField of Search340/347 AD, 340/347 SH, 375/39, 375/43, 375/54, 375/61, 375/75-77, 375/82, 375/86, 375/44, 375/102, 375/103, 375/57, 375/104, 375/99, 375/58, 455/46, 455/60, 455/63, 455/202, 455/205, 455/296, 455/307, 455/324, 455/315, 329/122, 329/50, 329/124, 329/153, 329/154, 364/721, 364/724, 364/724.1, 332/10, 332/44, 370/20, 341/110, 341/122US Class Current708/300CPC Class CodesH03B 27/00 Generation of oscillations ...H03B 28/00 Generation of oscillations ...H03C 3/40 using two signal paths the ...H03D 1/2245 using two quadrature channe...H03D 2200/005 Analog to digital conversionH03D 2200/0052 Digital to analog conversionH03D 3/006 by sampling the oscillation...H03D 3/007 by converting the oscillati...H03D 7/166 using two or more quadratur...
