Asynchronous digital arbiter
First Claim
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1. An asynchronous arbiter comprising:
- first and second input terminals for receiving the asynchronous signals to be arbitrated;
a first flip-flop having an input terminal connected by an inverter to the first input terminal, and having a clock terminal, an output terminal, an inverted output terminal, and a reset terminal;
a second flip-flop having an input terminal connected by an inverter to the second input terminal, and having a clock terminal, an output terminal, an inverted output terminal, and a reset terminal;
a first and second output logic means each having an output terminal and input terminals;
a logic means having input terminals and output terminals;
means connecting each of the first and second input terminals to, respectively, a first and a second input terminal of the logic means;
means connecting the inverted output terminals of the first and second flip-flops to, respectively, a third and a fourth input terminal of the logic means;
means connecting the input terminal of the first flip-flop to a first input terminal of the second output logic means;
means connecting the input terminal of the second flip-flop to a first input terminal of the first output logic means;
means connecting a first output terminal of the logic means to the clock terminals of the first and second flip-flops;
means connecting a second output terminal of the logic means to a second input terminal of, respectively, the first and second output logic means;
means connecting the output terminal of the first flip-flop to a third input terminal of, respectively, the first and second output logic means; and
means connecting the output terminal of the second flip-flop to a fourth input terminal of the first output logic means, so the output terminals of the first and second output logic means provide arbitrating signals between the first and second input signals.
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Abstract
An asynchronous digital arbiter circuit suitable for use in computer systems applications requiring fast asynchronous arbitration between two asynchronous inputs. The arbiter resolves which of two input signals is to be granted access, and provides a busy signal to the source of the other input signal. The arbiter consists solely of standard digital logic circuit elements including logic gates, flip-flops, and inverters.
32 Citations
16 Claims
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1. An asynchronous arbiter comprising:
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first and second input terminals for receiving the asynchronous signals to be arbitrated; a first flip-flop having an input terminal connected by an inverter to the first input terminal, and having a clock terminal, an output terminal, an inverted output terminal, and a reset terminal; a second flip-flop having an input terminal connected by an inverter to the second input terminal, and having a clock terminal, an output terminal, an inverted output terminal, and a reset terminal; a first and second output logic means each having an output terminal and input terminals; a logic means having input terminals and output terminals; means connecting each of the first and second input terminals to, respectively, a first and a second input terminal of the logic means; means connecting the inverted output terminals of the first and second flip-flops to, respectively, a third and a fourth input terminal of the logic means; means connecting the input terminal of the first flip-flop to a first input terminal of the second output logic means; means connecting the input terminal of the second flip-flop to a first input terminal of the first output logic means; means connecting a first output terminal of the logic means to the clock terminals of the first and second flip-flops; means connecting a second output terminal of the logic means to a second input terminal of, respectively, the first and second output logic means; means connecting the output terminal of the first flip-flop to a third input terminal of, respectively, the first and second output logic means; and means connecting the output terminal of the second flip-flop to a fourth input terminal of the first output logic means, so the output terminals of the first and second output logic means provide arbitrating signals between the first and second input signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An asynchronous arbiter comprising:
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a first memory element for receiving and storing a first input signal; a second memory element for receiving and storing a second input signal a logic means; means for providing the stored contents of the first and second memory elements to the logic means; first output logic means for inhibiting the first input signal; second output logic means for inhibiting the second input signal; means for providing an output of the logic means to the first and second memory elements so as to change the stored contents of the memory elements; means for providing an output of the logic means to the first and second output logic means; means for providing the stored contents of the first memory element to both the first and second output logic means; and means for providing the stored contents of the second memory element to the first output logic means. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification