Iopographic pattern delineated power mosfet with profile tailored recessed source
First Claim
1. A method employing no more than one independent mask of producing a plural-functional-region MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:
- forming over the oxide layer a dopant protective layer,creating a mask-surrogate pattern-definer having a defined outline characteristic in such protective layer,exposing a portion of the upper surface of the substrate within a range bounded by the defined outline characteristic,performing first and second doping steps in the exposed portion of the upper surface of the substrate to form a first diffusion of a first dopant type extending to a first depth within said region and to a first lateral width determined by the defined outline characteristic and to form a second diffusion of a second dopant type of polarity opposite the first dopant type and extending to a second depth within said region and a second lateral width determined by the defined outline characteristic,the second depth and width being less than the first depth and width, respectively, so that the second diffusion is contained within the first diffusion,forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed,the trench being formed to a trench depth less than the first diffusion depth and greater than the second diffusion depth and a trench width less than the second lateral width, so as to form separate source regions of the second diffusion along opposed sidewalls of the trench and to space the lower substrate surface of the base of the trench below the upper surface of the substrate,forming a gate conductive layer on the oxide layer and a source conductive layer on the base of the trench in contact with the lower substrate surface,the gate and source conductive layers each conforming to the defined outline characteristic and being spaced vertically apart by the spacing of the lower substrate surface on which the source conductive layer is deposited below the upper substrate surface portion on which the oxide layer is deposited, andthe source conductive layer and trench sidewalls being mutually formed so that the source conductive layer electrically contacts the source regions along said sidewalls.
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Accused Products
Abstract
A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O2 --SF6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.
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Citations
48 Claims
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1. A method employing no more than one independent mask of producing a plural-functional-region MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:
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forming over the oxide layer a dopant protective layer, creating a mask-surrogate pattern-definer having a defined outline characteristic in such protective layer, exposing a portion of the upper surface of the substrate within a range bounded by the defined outline characteristic, performing first and second doping steps in the exposed portion of the upper surface of the substrate to form a first diffusion of a first dopant type extending to a first depth within said region and to a first lateral width determined by the defined outline characteristic and to form a second diffusion of a second dopant type of polarity opposite the first dopant type and extending to a second depth within said region and a second lateral width determined by the defined outline characteristic, the second depth and width being less than the first depth and width, respectively, so that the second diffusion is contained within the first diffusion, forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed, the trench being formed to a trench depth less than the first diffusion depth and greater than the second diffusion depth and a trench width less than the second lateral width, so as to form separate source regions of the second diffusion along opposed sidewalls of the trench and to space the lower substrate surface of the base of the trench below the upper surface of the substrate, forming a gate conductive layer on the oxide layer and a source conductive layer on the base of the trench in contact with the lower substrate surface, the gate and source conductive layers each conforming to the defined outline characteristic and being spaced vertically apart by the spacing of the lower substrate surface on which the source conductive layer is deposited below the upper substrate surface portion on which the oxide layer is deposited, and the source conductive layer and trench sidewalls being mutually formed so that the source conductive layer electrically contacts the source regions along said sidewalls. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method employing no more than one independent mask of producing a plural-functional-region MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:
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forming over the oxide layer a dopant protective layer, creating a mask-surrogate pattern-definer having a defined outline characteristics in such protective layer, exposing a portion of the upper surface of the substrate within a region bounded by the defining outline characteristic, forming a sidewall spacer on each side of the mask surrogate pattern definer and underlying gate oxide with a predetermined thickness in contact with a margin of the exposed upper surface portion of the substrate to define a lateral offset from said defined outline characteristic; forming a trench in the exposed upper surface portion bounded by the sidewall spacer, the trench having a base defining a lower exposed portion of the substrate spaced below said upper surface and sidewalls that vertically separate the gate and source conductive layers; and forming a gate conductive layer on the oxide layer and a source conductive layer on the base of the trench in contact with the lower substrate surface, the gate and source conductive layers each conforming to the defined outline characteristic and being electrically separated along said sidewall spacer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A method of producing a transistor device on a semiconductor substrate upper surface, said method comprising:
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forming an oxide layer of a first predetermined thickness on the substrate upper surface, forming a protective layer of a second predetermined thickness over the oxide layer, patterning the protective layer in accordance with a defined outline characteristic, exposing a portion of the upper surface of the semiconductor substrate and opposite sides of the protective layer and underlying oxide layer along a boundary determined by the defined outline characteristic, forming a sidewall spacer on each side of the protective layer and underlying oxide layer with a predetermined thickness defining a lateral offset from said defined outline characteristic and a vertical dimension approximately equal to the sum of said first and second predetermined thickness, removing a portion of the protective layer to form a recess between the sidewall spacers, depositing a layer of conductive material to form a first conductive layer on the oxide layer within the recess and a second conductive layer on the exposed surface portion of the substrate, the first and second conductive layers being electrically separated laterally by the sidewall spacers, applying a planarizing layer after the steps of forming the sidewall spacers and depositing the conductive layers, removing a portion of the thickness of the planarizing material to expose any conductive material deposited atop the sidewall spacers, and removing any conductive deposited atop the sidewall spacers using the remaining thickness of the planarizing layer as a mask so as to leave separate layers of conductive material atop the oxide layer and the upper surface portion of the substrate. - View Dependent Claims (34, 35, 36, 37, 38, 39)
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40. A method of producing a vertical double-diffused MOSFET device on a semiconductor substrate upper surface, said method comprising:
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providing a silicon substrate having an upper surface, forming an oxide layer on the upper surface of the substrate, forming a dopant protective layer over the oxide layer, forming a mask surrogate pattern definer having a defined outline characteristic in such protective layer, exposing an upper surface portion of the substrate selectively within the defined outline characteristic, doping the substrate successively with the dopant ions of opposite polarity type to form a double-diffused, vertical field effect transistor positioned under the oxide layer and arranged to define a source region subjacent the defined outline characteristic, a drain region spaced laterally from the source beneath the oxide layer and extending downward into the bulk of the substrate, and a body region including a conduction channel positioned between the source and drain regions and operable upon inversion to conduct current between the source and drain regions, forming a trench in the exposed upper surface portion of the substrate having a sidewalls and a base defining an exposed lower surface portion of the substrate, the trench extending depthwise through the source region to expose the body region in the base thereof, and forming a gate conductive layer on the oxide layer and a source conductive layer on the base of the trench and in electrical contact with the source and body regions, the doping step including introducing dopant ions for the source region prior to the trench-forming step. - View Dependent Claims (41, 42)
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43. A method of producing a vertical double-diffused MOSFET device on a semiconductor substrate upper surface, said method comprising:
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providing a silicon substrate having an inner surface, forming an oxide layer on the upper surface of the substrate, forming a dopant protective layer over the oxide layer, forming a mask surrogate pattern definer having a defined outline characteristic in such protective layer, exposing an upper surface portion of the substrate selectively within the defined outline characteristic, doping the substrate successively with the dopant ions of opposite polarity type to form a double-diffused, vertical field effect transistor positioned under the oxide layer and arranged to define a source region subjacent the defined outline characteristic, a drain region spaced laterally from the source beneath the oxide layer and extending downward into the bulk of the substrate, and a conduction channel positioned between the source and a drain regions and operable upon inversion to conduct current between the source and drain regions, forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed, and forming a gate conductive layer in the oxide layer and a source conductive layer on at least the base of the trench; the doping step including first and second doping steps, performed prior to forming the trench, to introduce ions of a first dopant type to a first depth within said region and to a first lateral width determined by the defined outline characteristic and to introduce ions of a second dopant type of polarity opposite the first dopant type to a second depth within said region and a second lateral width determining by the defined outline characteristic; the second depth and width being less than the first depth and width, respectively, so that the doped region of the second type is contained within the doped region of the first type; the trenching being formed to a trench depth less than the depth of the first doped region and greater than the depth of the second doped region and a trench width less than the lateral width of the second doped region, so as to form separate source regions of the second dopant type along opposed sidewalls of the trench; and the source conductive layer being formed so as to electrically contact the source regions along said sidewalls.
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44. A method of producing a vertical double-diffused MOSFET device on a semiconductor substrate upper surface, said method comprising:
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providing a silicon substrate having an upper surface, forming an oxide layer on the upper surface of the substrate, forming a dopant protective layer over the oxide layer, forming a mask surrogate pattern definer having a defined outline characteristic in such protective layer, exposing an upper surface portion of the substrate selectively within the defined outline characteristic, doping the substrate successively with the dopant ions of opposite polarity type to form a double-diffusion, vertical field effect transistor positioned under the oxide layer and arranged to define a source region subjacent the defined outline characteristic, a drain region spaced laterally from the source beneath the oxide layer and extending downward into the bulk of the substrate, and a conduction channel positioned between the source and drain regions and operable upon inversion to conduct Current between the source and drain regions, forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed, and forming a gate conductive layer on the oxide layer and a source conductive layer on at least the base of the trench; the doping step including introducing dopant ions for the source region prior to the trench-forming step and a third doping step, following forming of the trench, to form a third doped region of additional first dopant type in the substrate in the base of the trench, and codiffusing the additional first dopant type and the second dopant type after trenching, the diffusion of the additional first dopant type limiting the extent of downward diffusion of the second dopant type and increasing the conductivity of the first dopant type beneath the trench and a portion of the second doped region.
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45. A method of producing a vertical double-diffused MOSFET device on a semiconductor substrate upper surface, said method comprising:
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providing a silicon substrate having an upper surface, forming an oxide layer on the upper surface of the substrate, forming a dopant protective layer over the oxide layer, forming a mask surrogate pattern definer having a defined outline characteristic in such protective layer, exposing an upper surface portion of the substrate selectively within the defined outlined characteristic, doping the substrate successively with the dopant ions of opposite polarity type to form a double-diffused, vertical field effect transistor positioned under the oxide layer and arranged to define a source region subjacent the defined outline characteristic, a drain region spaced laterally from the source beneath the oxide layer and extending downward into the bulk of the substrate, and a conduction channel positioned between the source and drain regions and operable upon inversion to conduct current between the source and drain regions, forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed, and forming a gate conductive layer on the oxide layer and a source conductive layer on at least the base of the trench, the doping step including introducing dopant ions for the source region prior to the trench-forming step, and forming a low resistivity contact layer on at least the sidewalls of the trench after the trench-forming step and prior to depositing the source conductive layer to electrically interconnect the source region and the source conductive layer.
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46. A method of producing a transistor device on a semiconductor substrate upper surface, said method comprising:
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forming an oxide layer of a first predetermined thickness on the substrate upper surface, forming a protective layer of a second predetermined thickness over the oxide layer, patterning the protective layer in accordance with a defined outline characteristic, exposing a portion of the upper surface of the semiconductor substrate and opposite sides of the protective layer and underlying oxide layer along a boundary determined by the defined outline characteristic, forming a sidewall spacer on each side of the protective layer and underlying oxide layer with a predetermined thickness defining a lateral offset from said defined outline characteristic and a vertical dimension approximately equal to the sum of said first and second predetermined thicknesses, removing a portion of the protective layer to form a recess between the sidewall spacers and forming a trench in the exposed upper substrate surface portion bounded by the sidewall spacers, the trench having a base with a lower exposed substrate spaced below the upper substrate surface, depositing a layer of conductive material to form a first conductive layer on the oxide layer within the recess and a second conductive layer on the lower exposed substrate surface, the first and second conductive layers being electrically separated laterally by the sidewall spacers and vertically by the elevation of the upper and lower substrate surfaces. - View Dependent Claims (47, 48)
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Specification