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Iopographic pattern delineated power mosfet with profile tailored recessed source

  • US 4,895,810 A
  • Filed: 05/17/1988
  • Issued: 01/23/1990
  • Est. Priority Date: 03/21/1986
  • Status: Expired due to Term
First Claim
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1. A method employing no more than one independent mask of producing a plural-functional-region MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:

  • forming over the oxide layer a dopant protective layer,creating a mask-surrogate pattern-definer having a defined outline characteristic in such protective layer,exposing a portion of the upper surface of the substrate within a range bounded by the defined outline characteristic,performing first and second doping steps in the exposed portion of the upper surface of the substrate to form a first diffusion of a first dopant type extending to a first depth within said region and to a first lateral width determined by the defined outline characteristic and to form a second diffusion of a second dopant type of polarity opposite the first dopant type and extending to a second depth within said region and a second lateral width determined by the defined outline characteristic,the second depth and width being less than the first depth and width, respectively, so that the second diffusion is contained within the first diffusion,forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed,the trench being formed to a trench depth less than the first diffusion depth and greater than the second diffusion depth and a trench width less than the second lateral width, so as to form separate source regions of the second diffusion along opposed sidewalls of the trench and to space the lower substrate surface of the base of the trench below the upper surface of the substrate,forming a gate conductive layer on the oxide layer and a source conductive layer on the base of the trench in contact with the lower substrate surface,the gate and source conductive layers each conforming to the defined outline characteristic and being spaced vertically apart by the spacing of the lower substrate surface on which the source conductive layer is deposited below the upper substrate surface portion on which the oxide layer is deposited, andthe source conductive layer and trench sidewalls being mutually formed so that the source conductive layer electrically contacts the source regions along said sidewalls.

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