Iopographic pattern delineated power mosfet with profile tailored recessed source

• US 4,895,810 A
• Filed: 05/17/1988
• Issued: 01/23/1990
• Est. Priority Date: 03/21/1986
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Meyer, Theodore O., Pike, Douglas A. Jr., Mosier, John W. II, Hollinger, Theodore G.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, T.
• Application Number:
  US07/194,874
• Time in Patent Office: 616 Days
• Field of Search: 437/41, 437/38, 437/192, 437/193, 437/200, 437/203, 437/228, 437/245, 437/249, 357/23.1, 357/23.4, 357/37, 357/55, 156/643, 156/644
• US Class Current: 438/274
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O₂ --SF₆ plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.

Claims

1. A method employing no more than one independent mask of producing a plural-functional-region MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:

forming over the oxide layer a dopant protective layer,

creating a mask-surrogate pattern-definer having a defined outline characteristic in such protective layer,

exposing a portion of the upper surface of the substrate within a range bounded by the defined outline characteristic,

performing first and second doping steps in the exposed portion of the upper surface of the substrate to form a first diffusion of a first dopant type extending to a first depth within said region and to a first lateral width determined by the defined outline characteristic and to form a second diffusion of a second dopant type of polarity opposite the first dopant type and extending to a second depth within said region and a second lateral width determined by the defined outline characteristic,

the second depth and width being less than the first depth and width, respectively, so that the second diffusion is contained within the first diffusion,

forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed,

the trench being formed to a trench depth less than the first diffusion depth and greater than the second diffusion depth and a trench width less than the second lateral width, so as to form separate source regions of the second diffusion along opposed sidewalls of the trench and to space the lower substrate surface of the base of the trench below the upper surface of the substrate,

forming a gate conductive layer on the oxide layer and a source conductive layer on the base of the trench in contact with the lower substrate surface,

the gate and source conductive layers each conforming to the defined outline characteristic and being spaced vertically apart by the spacing of the lower substrate surface on which the source conductive layer is deposited below the upper substrate surface portion on which the oxide layer is deposited, and

the source conductive layer and trench sidewalls being mutually formed so that the source conductive layer electrically contacts the source regions along said sidewalls.

2. A method according to claim 1 in which the second diffusion is formed in two separate steps, including introducing the second dopant to the substrate prior to trenching and diffusing the second dopant after trenching.

3. A method according to claim 2 in which introducing the second dopant causes defects in the exposed upper surface portion of the substrate and the trenching substantially reduces said defects and the likelihood of defects occurring in a subsequent diffusion.

4. A method according to claim 1 including a third doping step, following forming the trench, to form a third diffusion of the first dopant type in the substrate in the base of the trench, the third diffusion limiting the extent of downward diffusion of the second dopant type and increasing the conductivity of the first dopant type beneath the trench and second diffusion.

5. A method according to claim 1 in which the second diffusion is formed in separate first and second substeps, including:

a first substep of introducing the second dopant to the substrate prior to trenching;

a third doping step, following forming the trench, to introduce additional dopant of the first type into the substrate in the base of the trench; and

a second substep of codiffusing the additional dopant of the first type and the second dopant type after trenching, the diffusion of the additional dopant of the first type limiting the extent of downward diffusion of the second dopant type and increasing the conductivity of the first dopant type beneath the trench and a portion of the second diffusion.

6. A method according to claim 1 in which the trench sidewalls are profile-tailored such that a portion of the trench sidewalls is shielded from deposition of the conductive layers.

7. A method according to claim 6 in which the sidewalls are formed in a stairstep profile to provide a recess defining the shielded portion immediately subjacent an edge of the sidewall spacer and a step in the trench sidewall that is substantially aligned with the edge of the sidewall spacer.

8. A method according to claim 1 including forming a low-resistivity contact layer on at least the trench sidewalls and extending between the source region and the source conductive layer.

9. A method according to claim 8 in which the low resistivity contact layer is formed by diffusion of additional dopant of the second dopant type.

10. A method according to claim 8 in which the low resistivity contact layer is formed by selective deposition of one of a refractory metal and a metal silicide.

11. A method employing no more than one independent mask of producing a plural-functional-region MOS semiconductor device in a substrate structure including a gate oxide layer on an upper surface of a semiconductor substrate, said method comprising:

forming over the oxide layer a dopant protective layer,

creating a mask-surrogate pattern-definer having a defined outline characteristics in such protective layer,

exposing a portion of the upper surface of the substrate within a region bounded by the defining outline characteristic,

forming a sidewall spacer on each side of the mask surrogate pattern definer and underlying gate oxide with a predetermined thickness in contact with a margin of the exposed upper surface portion of the substrate to define a lateral offset from said defined outline characteristic;

forming a trench in the exposed upper surface portion bounded by the sidewall spacer, the trench having a base defining a lower exposed portion of the substrate spaced below said upper surface and sidewalls that vertically separate the gate and source conductive layers; and

forming a gate conductive layer on the oxide layer and a source conductive layer on the base of the trench in contact with the lower substrate surface,

the gate and source conductive layers each conforming to the defined outline characteristic and being electrically separated along said sidewall spacer.

12. A method according to claim 11 in which:

the doping step includes first and second doping steps, performed prior to forming the trench, to form a first diffusion of a first dopant type extending to a first depth within said region and to a first lateral width determined by the defined outline characteristic and to form a second diffusion of a second dopant type of polarity opposite the first dopant type and extending to a second depth within said region and a second lateral width determined by the defined outline characteristic;

the second depth and width being less than the first depth and width, respectively, so that the second diffusion is contained within the first diffusion;

the trench being formed to a trench the first diffusion depth and greater than the second diffusion depth and a trench width less than the second lateral width, so as to form separate source regions of the second diffusion along opposed sidewalls of the trench; and

the source conductive layer being formed so as to electrically contact the source regions along said sidewalls.

13. A method according to claim 12 in which the second diffusion is formed in two separate steps, including introducing the second dopant to the substrate prior to trenching and diffusing the second dopant after trenching.

14. A method according to claim 13 in which introducing the second dopant causes defects in the exposed upper surface portion of the substrate and the trenching substantially reduces said defects and the likelihood of defects occurring in a subsequent diffusion.

15. A method according to claim 12 including a third doping step, following forming the trench, to form a third diffusion of the first dopant type in the substrate in the base of the trench, the third diffusion limiting the extent of downward diffusion of the second dopant type and increasing the concentration of the first dopant type beneath the trench and a portion of the second diffusion.

16. A method according to claim 12 in which the second diffusion is formed in separate first and second substeps, including:

a first substep of introducing the second dopant to the substrate prior to trenching;

a third doping step, following forming the trench, to introduce additional dopant of the first type into the substrate in the base of the trench; and

a second substep of codiffusing the additional dopant of the first type and the second dopant type after trenching, the diffusion of the additional dopant of the first type limiting the extent of downward diffusion of the second dopant type and increasing the conductivity of the first dopant type beneath the trench and a portion of the second diffusion.

17. A method according to claim 11 in which the doping step includes diffusing a dopant to form source regions in the substrate along the trench sidewalls and beneath the sidewall spacers and mutually sizing the sidewall spacer thickness and the trench width to laterally position the source regions beneath the sidewall spacers and a margin of the gate oxide and to control the width of the source regions.

18. A method according to claim 17 in which the sidewall spacer is sized to a thickness in the range of 0.1 to 1.0 micrometers and the trench sidewalls are profile-tailored to form a recess extending part way beneath the sidewall spacers.

19. A method according to claim 18 including forming a low-resistivity contact layer in the recess and extending between the source region and the source conductive layer.

20. A method according to claim 17 in which the sidewall spacer is sized to a thickness in the range of 0.1 to 0.2 micrometers and the trench sidewalls are profile-tailored so to be substantially aligned with the sidewall spacers.

21. A method according to claim 20 including forming a low-resistivity contact layer on at least the trench sidewalls and extending between the source region and the source conductive layer.

22. A method according to claim 21 including forming a second sidewall spacer over the low resistivity contact layer and prior to depositing the source conductive layer.

23. A method according to claim 17 in which the trench sidewalls are profile-tailored such that a portion of the trench sidewalls is shielded from said conductive material deposition, including forming a low-resistivity contact layer on at least the trench sidewalls and extending between the source region and the source conductive layer.

24. A method according to claim 23 in which the sidewalls are formed in a stairstep profile to provide a recess defining the shielded portion immediately subjacent an edge of the sidewall spacer and a step in the trench sidewall that is substantially aligned with the edge of the sidewall spacer.

25. A method according to claim 23 in which the recess has a lateral dimension approximately half the thickness of the sidewall spacer.

26. A method according to claim 25 including selecting a slowly diffusing element as the dopant.

27. A method according to claim 17 including controlling the rate of diffusion of the dopant to limit the width of the source regions.

28. A method according to claim 11 including:

applying a planarizing layer after the steps of forming the sidewall spacer and trench and the conductive-material deposition step,

removing a portion of the thickness of the planarizing material to expose any conductive material deposited atop the sidewall spacers, and

removing the conductive material deposited atop the sidewall spacers using the remaining thickness of the planarizing layer as a mask so as to leave separate layers of conductive material atop the gate oxide and in the trench.

29. A method according to claim 28 in which the mask surrogate pattern definer comprises a polysilicon layer and at least a portion thereof is removed during the trench-forming step, so that the sidewall spacer and any conductive material deposited thereon tend to protrude above adjacent structures into the planarizing layer.

30. A method according to claim 29 in which deposition of the conductive material includes selective deposition of metal or metal silicide solely on the exposed substrate surfaces, within the trench and on the polysilicon.

31. A method according to claim 29 in which the polysilicon layer is formed as a first, doped polysilicon layer in contact with the oxide layer, a second polysilicon layer atop the first polysilicon layer, and an etch-stopping layer sandwiched between the first and second layers to limit removal to the second polysilicon layer.

32. A method according to claim 28 in which the mask surrogate pattern definer is polysilicon and the trench-forming step includes removing at least a portion of the polysilicon, whereby the sidewall spacer and any conductive material deposited thereon tend to protrude above adjacent structures into the planarizing layer.

33. A method of producing a transistor device on a semiconductor substrate upper surface, said method comprising:

forming an oxide layer of a first predetermined thickness on the substrate upper surface,

forming a protective layer of a second predetermined thickness over the oxide layer,

patterning the protective layer in accordance with a defined outline characteristic,

exposing a portion of the upper surface of the semiconductor substrate and opposite sides of the protective layer and underlying oxide layer along a boundary determined by the defined outline characteristic,

forming a sidewall spacer on each side of the protective layer and underlying oxide layer with a predetermined thickness defining a lateral offset from said defined outline characteristic and a vertical dimension approximately equal to the sum of said first and second predetermined thickness,

removing a portion of the protective layer to form a recess between the sidewall spacers,

depositing a layer of conductive material to form a first conductive layer on the oxide layer within the recess and a second conductive layer on the exposed surface portion of the substrate, the first and second conductive layers being electrically separated laterally by the sidewall spacers,

applying a planarizing layer after the steps of forming the sidewall spacers and depositing the conductive layers,

removing a portion of the thickness of the planarizing material to expose any conductive material deposited atop the sidewall spacers, and

removing any conductive deposited atop the sidewall spacers using the remaining thickness of the planarizing layer as a mask so as to leave separate layers of conductive material atop the oxide layer and the upper surface portion of the substrate.

34. A method according to claim 33 including spacing the exposed upper surface portion vertically relative to a surface in the recess between sidewall spacers so as to space the conductive layers vertically apart.

35. A method according to claim 34 in which the spacing step is performed by forming a trench in the exposed upper surface portion bounded by the sidewall spacers, the trench having a base and sidewalls that vertically separate the first and second conductive layers.

36. A method according to claim 35 in which the protective layer comprises a polysilicon layer and at least a portion thereof is removed during the trench-forming step.

37. A method according to claim 36 in which deposition of the conductive material includes selective deposition of metal or metal silicide solely on the exposed substrate surfaces within the trench and on the polysilicon.

38. A method according to claim 36 in which the polysilicon layer is formed as a first, doped polysilicon layer in contact with the oxide layer, a second polysilicon layer atop the first polysilicon layer, and an etch-stopping layer sandwiched between the first and second layers to limit removal to the second polysilicon layer.

39. A method according to claim 35 in which the protective layer comprises a polysilicon layer and the trench-forming step includes removing at least a portion of the polysilicon layer so that the sidewall spacer and any conductive material deposited thereon tend to protrude above adjacent structures into the planarizing layer.

40. A method of producing a vertical double-diffused MOSFET device on a semiconductor substrate upper surface, said method comprising:

providing a silicon substrate having an upper surface,

forming an oxide layer on the upper surface of the substrate,

forming a dopant protective layer over the oxide layer,

forming a mask surrogate pattern definer having a defined outline characteristic in such protective layer,

exposing an upper surface portion of the substrate selectively within the defined outline characteristic,

doping the substrate successively with the dopant ions of opposite polarity type to form a double-diffused, vertical field effect transistor positioned under the oxide layer and arranged to define a source region subjacent the defined outline characteristic, a drain region spaced laterally from the source beneath the oxide layer and extending downward into the bulk of the substrate, and a body region including a conduction channel positioned between the source and drain regions and operable upon inversion to conduct current between the source and drain regions,

forming a trench in the exposed upper surface portion of the substrate having a sidewalls and a base defining an exposed lower surface portion of the substrate, the trench extending depthwise through the source region to expose the body region in the base thereof, and

forming a gate conductive layer on the oxide layer and a source conductive layer on the base of the trench and in electrical contact with the source and body regions,

the doping step including introducing dopant ions for the source region prior to the trench-forming step.

41. A method according to claim 40 in which the dopant ions are diffused after the trench-forming step.

42. A method according to claim 40 including a third doping step, following forming the trench, to form a third dopant region of additional first dopant type in the substrate in the base of the trench.

43. A method of producing a vertical double-diffused MOSFET device on a semiconductor substrate upper surface, said method comprising:

providing a silicon substrate having an inner surface,

forming an oxide layer on the upper surface of the substrate,

forming a dopant protective layer over the oxide layer,

forming a mask surrogate pattern definer having a defined outline characteristic in such protective layer,

exposing an upper surface portion of the substrate selectively within the defined outline characteristic,

doping the substrate successively with the dopant ions of opposite polarity type to form a double-diffused, vertical field effect transistor positioned under the oxide layer and arranged to define a source region subjacent the defined outline characteristic, a drain region spaced laterally from the source beneath the oxide layer and extending downward into the bulk of the substrate, and a conduction channel positioned between the source and a drain regions and operable upon inversion to conduct current between the source and drain regions,

forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed, and

forming a gate conductive layer in the oxide layer and a source conductive layer on at least the base of the trench;

the doping step including first and second doping steps, performed prior to forming the trench, to introduce ions of a first dopant type to a first depth within said region and to a first lateral width determined by the defined outline characteristic and to introduce ions of a second dopant type of polarity opposite the first dopant type to a second depth within said region and a second lateral width determining by the defined outline characteristic;

the second depth and width being less than the first depth and width, respectively, so that the doped region of the second type is contained within the doped region of the first type;

the trenching being formed to a trench depth less than the depth of the first doped region and greater than the depth of the second doped region and a trench width less than the lateral width of the second doped region, so as to form separate source regions of the second dopant type along opposed sidewalls of the trench; and

the source conductive layer being formed so as to electrically contact the source regions along said sidewalls.

44. A method of producing a vertical double-diffused MOSFET device on a semiconductor substrate upper surface, said method comprising:

providing a silicon substrate having an upper surface,

forming an oxide layer on the upper surface of the substrate,

forming a dopant protective layer over the oxide layer,

forming a mask surrogate pattern definer having a defined outline characteristic in such protective layer,

exposing an upper surface portion of the substrate selectively within the defined outline characteristic,

doping the substrate successively with the dopant ions of opposite polarity type to form a double-diffusion, vertical field effect transistor positioned under the oxide layer and arranged to define a source region subjacent the defined outline characteristic, a drain region spaced laterally from the source beneath the oxide layer and extending downward into the bulk of the substrate, and a conduction channel positioned between the source and drain regions and operable upon inversion to conduct Current between the source and drain regions,

forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed, and

forming a gate conductive layer on the oxide layer and a source conductive layer on at least the base of the trench;

the doping step including introducing dopant ions for the source region prior to the trench-forming step and a third doping step, following forming of the trench, to form a third doped region of additional first dopant type in the substrate in the base of the trench, and

codiffusing the additional first dopant type and the second dopant type after trenching, the diffusion of the additional first dopant type limiting the extent of downward diffusion of the second dopant type and increasing the conductivity of the first dopant type beneath the trench and a portion of the second doped region.

45. A method of producing a vertical double-diffused MOSFET device on a semiconductor substrate upper surface, said method comprising:

providing a silicon substrate having an upper surface,

forming an oxide layer on the upper surface of the substrate,

forming a dopant protective layer over the oxide layer,

forming a mask surrogate pattern definer having a defined outline characteristic in such protective layer,

exposing an upper surface portion of the substrate selectively within the defined outlined characteristic,

doping the substrate successively with the dopant ions of opposite polarity type to form a double-diffused, vertical field effect transistor positioned under the oxide layer and arranged to define a source region subjacent the defined outline characteristic, a drain region spaced laterally from the source beneath the oxide layer and extending downward into the bulk of the substrate, and a conduction channel positioned between the source and drain regions and operable upon inversion to conduct current between the source and drain regions,

forming a trench in the exposed upper surface portion of the substrate, the trench having a base and sidewalls in which a lower substrate surface is exposed, and forming a gate conductive layer on the oxide layer and a source conductive layer on at least the base of the trench,

the doping step including introducing dopant ions for the source region prior to the trench-forming step, and

forming a low resistivity contact layer on at least the sidewalls of the trench after the trench-forming step and prior to depositing the source conductive layer to electrically interconnect the source region and the source conductive layer.

46. A method of producing a transistor device on a semiconductor substrate upper surface, said method comprising:

forming an oxide layer of a first predetermined thickness on the substrate upper surface,

forming a protective layer of a second predetermined thickness over the oxide layer,

patterning the protective layer in accordance with a defined outline characteristic,

exposing a portion of the upper surface of the semiconductor substrate and opposite sides of the protective layer and underlying oxide layer along a boundary determined by the defined outline characteristic,

forming a sidewall spacer on each side of the protective layer and underlying oxide layer with a predetermined thickness defining a lateral offset from said defined outline characteristic and a vertical dimension approximately equal to the sum of said first and second predetermined thicknesses,

removing a portion of the protective layer to form a recess between the sidewall spacers and forming a trench in the exposed upper substrate surface portion bounded by the sidewall spacers, the trench having a base with a lower exposed substrate spaced below the upper substrate surface,

depositing a layer of conductive material to form a first conductive layer on the oxide layer within the recess and a second conductive layer on the lower exposed substrate surface, the first and second conductive layers being electrically separated laterally by the sidewall spacers and vertically by the elevation of the upper and lower substrate surfaces.

47. A method according to claim 46 in which dopant ions of a first dopant type are introduced to the exposed portion of substrate prior to the trench-forming step and diffused after the trench-forming step to form laterally separated doped source regions in the substrate along each sidewall of the trench.

48. A method according to claim 47 in which, after forming the trench, dopant ions of a second dopant type of opposite polarity from the ions of first dopant type are introduced into the exposed substrate in the base of the trench and then diffused to limit downward diffusion of the source regions.