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Fault management system for a switched reluctance motor

  • US 4,896,089 A
  • Filed: 01/31/1989
  • Issued: 01/23/1990
  • Est. Priority Date: 01/31/1989
  • Status: Expired due to Fees
First Claim
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1. A fault management system for detecting faults in a multiphase switched reluctance motor employing unidirectional current excitation from a DC source, each phase of said motor comprising two stator poles and a phase winding having two motor leads for connecting the phase winding in series with at least one respective semiconductor switch, said system further isolating any detected faults so that the faulted motor phases are deactivated and motor operation is continued through the remaining phases, said system comprising:

  • a plurality of phase control circuits, said phase control circuits each comprising a respective AND gate coupled to a separate respective semiconductor switch, each AND gate generating a low logic level output signal when a fault is detected in the corresponding motor phase, whereby each motor phase exhibiting a fault is deactivated;

    a plurality of current sensor means, each respective one of said current sensor means coupled to a separate respective semiconductor switch to sense the instantaneous current in the respective motor phase winding, the output of each of said current sensor means, respectively, coupled to an input of the AND gate of the corresponding phase control circuit, each respective one of said current sensor means generating a low logic level output signal to the AND gate of the corresponding phase control circuit whenever the respective instantaneous phase current exceeds a regulated current limit; and

    a plurality of current differential sensor means, each respective one of said current differential sensor means coupled to a separate respective motor phase winding for detecting any difference in current flow between the two leads of each respective phase winding of the corresponding phase, the output of each of said current differential sensor means, respectively, coupled to an input of the AND gate of the corresponding phase control circuit, each respective one of said current differential sensor means generating a low logic level signal output to the AND gate of the corresponding phase control circuit when any difference in current flow between the two leads of each respective phase winding of the corresponding phase is detected.

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