Switched-capacitance coupling networks for differential-input amplifiers, not requiring balanced input signals

• US 4,896,156 A
• Filed: 10/03/1988
• Issued: 01/23/1990
• Est. Priority Date: 10/03/1988
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Garverick, Steven L.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Young, Brian K.
• Application Number:
  US07/252,484
• Time in Patent Office: 477 Days
• Field of Search: 341/122, 341/143, 341/144, 341/155, 341/158, 341/167, 341/172, 332/11 D, 375/26, 375/27, 375/28, 375/33
• US Class Current: 341/143
• CPC Class Codes: G06G 7/1865 with initial condition setting
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path
• CPC Class Codes: H03M 3/496 Details of sampling arrangements or methods

Abstract

A differential delta-sigma modulator of switched-capacitance type is operated with a three-phase cycle, rather than the two-phase cycle of the prior art. In the first phase of operation the switched capacitors are charged in accordance with the previous single-bit output of the modulator. Structural modifications permit the switching capacitors to be connected in series to receive the modulator input voltage during the second phase of operation so that voltage need not be balanced with regard to any specified common-mode potential. In the third phase of operation the switched capacitors discharge from first plates thereof to the differential-input integrator while the second plates thereof are driven in accordance with the previous single-bit output of the modulator.

Claims

1. A switched-capacitance coupling network responsive to the difference between voltages appearing respectively at first and second nodes for applying that difference between first and second input connections of a differential amplifier, said switched capacitor apparatus comprising:

a third node for receiving a common-mode voltage;

fourth and fifth nodes for receiving respective voltages, one of which is positive in a given amount respective to said common-mode voltage and the other of which is negative in said given amount respective to said common-mode voltage, at any given time;

a first capacitor having respective first and second plates;

a second capacitor having respective first and second plates;

means for generating in staggered phase relationship a first train of pulses, a second train of pulses and a third train of pulses, pulses of which trains occur cyclically in order of their train number and do not overlap;

means for selectively connecting the first plates of said first and second capacitors to said third node only during each pulse of said first train;

means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second nodes only during each pulse of said second train;

means for selectively connecting the first plates of said first and second capacitors to separate ones of first and second input connections of said differential amplifier, only during each pulse of said third train;

means for selectively connecting the second plates of said first and second capacitors to separate ones of said fourth and fifth nodes only during intervals between pulses in said second train including times when pulses appear in said first train and times when pulses appear in said third train; and

means for selectively connecting the first plates of said first and second capacitors solely to each other during each pulse of said second train and disconnecting them from each other at least at times their second plates are connected to said fourth and fifth nodes, respectively.

2. A switched-capacitor coupling network as set forth in claim 1, wherein said means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second nodes is of a type that invariably connects the second plates of said first and second capacitors to said first node and to said second node, respectively;

wherein said means for selectively connecting the first plates of said first and second capacitors to separate ones of the first and second input connections of said differential amplifier is of a type that invariably connects the first plates of said first and second capacitors to the first and second input connections, respectively, of said differential amplifier; and

wherein said means for selectively connecting the second plates of said first and second capacitors to separate ones of said fourth and fifth nodes is of a type that invariably connects the second plates of said first and second capacitors to said fourth node and to said fifth node, respectively.

3. A switched-capacitance coupling network as set forth in claim 1 having supplied thereto a control signal alternating at regular rate between first and second levels;

wherein said means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second nodes essentially consists of;

means for selectively connecting the second plates of said first and second capacitors to said first and second nodes, respectively, only during each pulse of said second train and said first level of said control signal; and

means for selectively connecting the second plates of said first and second capacitors to said second and first nodes, respectively, only during each pulse of said second train and said second level of said control signal.

4. A switched-capacitance coupling network as set forth in claim 3 wherein said means for selectively connecting the second plates of said first and second capacitors to separate ones of said fourth and fifth nodes is of a type that invariably connects the second plates of said first and second capacitors to said fourth node and to said fifth node respectively.

5. A switched-capacitance coupling network as set forth in claim 4 wherein said means for selectively connecting the first plates of said first and second capacitors to separate ones of the first and second input connections of said differential amplifier essentially consists of:

means for selectively connecting the first plates of said first and second capacitors respectively to said first and said second input connections of said differential amplifier only during each pulse of said third train and said first level of said control signal; and

means for selectively connecting the first plates of said first and second capacitors respectively to said second and said first input connections of said differential amplifier only during each pulse of said third train and said second level of said control signal.

6. A switched-capacitance coupling network as set forth in claim 1 included in a delta-sigma modulator that also comprises:

said differential amplifier having first and second output connections, its said first and second input connections being respectively inverting and non-inverting respective to said first output connection and being respectively non-inverting and inverting respective to said second input connection;

means connecting said differential amplifier as a differential Miller integrator, which means includes

a first Miller feedback connection between the first output and first input connections of said differential amplifier, and

a second Miller feedback connection between the second output and second input connections of said differential amplifier;

third and fourth capacitors respectively providing separate ones of said first and second Miller feedback connectors, at any given time; and

an analog-to-digital converter for resolving voltage appearing between the first and second output connections of said differential amplifier to a single-bit output signal applied as said respective voltages to said fourth node and to said fifth node.

7. A delta-sigma modulator as set forth in claim 6;

wherein said first Miller feedback connection includes said third capacitor having a first plate invariably connected to the first output connection of said differential amplifier and having a second plate invariably connected to the first input connection of said differential amplifier; and

wherein said second Miller feedback connection includes said fourth capacitor having a first plate invariably connected to the second output connection of said differential amplifier and having a second plate invariably connected to the second input connection of said differential amplifier.

8. A delta-sigma modulator as set forth in claim 6 having:

means for selectively connecting said third capacitor and said fourth capacitor in said first Miller feedback connection and in said second Miller feedback connection respectively during one half of each analog-to-digital conversion; and

means for selectively connecting said third capacitor and said fourth capacitor in said second Miller feedback connection and in said first Miller feedback connection respectively during the remaining half of each analog-to-digital conversion.

9. A differential delta-sigma modulator comprising:

first and second input terminals;

a first capacitor having respective first and second plates;

a second capacitor having respective first and second plates;

a differential amplifier having first and second output connections and having first and second input connections that are respectively inverting and non-inverting input connections insofar as said first output connection is concerned and are respectively non-inverting and inverting input connections insofar as said second output connection is concerned;

a third capacitor connected between the first output connection and first input connection of said differential amplifier;

a fourth capacitor connected between the second output connection and second input connection of said differential amplifier;

an analog-to-digital converter for resolving the voltage between the first and second output connections of said differential amplifier to a single-bit output signal supplied in push-pull at first and second output connections thereof;

means for generating in staggered phase relationship a first train of pulses, a second train of pulses and a third train of pulses, pulses of which said trains occur cyclically in order of their train number and do not overlap;

means for selectively connecting the first plates of said first and second capacitors to a common-mode potential only during each pulse of said first train;

means for selectively connecting the second plates of said first and second capacitors to said first and second input terminals, respectively, only during each pulse of said second train;

means for selectively connecting the first plates of said first and second capacitors to the first and second input connections of said differential amplifier, respectively, only during each pulse of said third train;

means for selectively connecting said second plates of said first and second capacitors to respective ones of the first and second output connections of said analog-to-digital converter only during intervals between pulses in said second train including times when pulses appear in said first train and times when pulses appear in said third train; and

means for selectively connecting the first plates of said first and second capacitors solely to each other during each pulse of said second traind and disconnecting them from each other at least at times their second plates are connected to respective ones of the first and second output connections of said analog-to-digital converter.

10. A differential delta-sigma modulator for performing analog-to-digital conversions each having respective first and second portions of similar duration, said differential delta-sigma modulator comprising:

first and second input terminals;

a first capacitor having respective first and second plates;

a second capacitor having respective first and second plates;

a differential amplifier having first and second output connections and having first and second input connections that are respectively inverting and non-inverting input connections insofar as said first output connection is concerned and are respectively non-inverting and inverting input connections insofar as said second output connection is concerned;

a third capacitor connected between the first output connection and first input connection of said differential amplifier;

a fourth capacitor connected between the second output connection and second input connection of said differential amplifier;

an analog-to-digital converter for resolving the voltage between the first and second output connections of said differential amplifier to a single-bit output signal supplied in push-pull at first and second output connections thereof;

means for generating in staggered phase relationship a first train of pulses, a second train of pulses and a third train of pulses, pulses of which said trains occur cyclically in order of their train number and do not overlap;

means for selectively connecting the first plates of said first and second capacitors to a common-mode potential only during each pulse of said first train;

means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second terminals only during each pulse of said second train;

means for selectively connecting the first plates of said first and second capacitors to the first and second input connections of said differential amplifier, respectively, only during each pulse of said third train in said first portions of analog-to-digital conversions;

means for selectively connecting the first plates of said first and second capacitors to the second and first input connections of said differential amplifier, respectively, only during each pulse of said third train in said second portions of analog-to-digital conversions;

means for selectively connecting said second plates of said first and second capacitors to separate ones of the first and second output connections of said analog-to-digital converter only during intervals between pulses in said second train including times when pulses appear in said first train and times when pulses appear in said third train, connection being one way during said first portions of analog-to-digital conversions and being the other way during said second portions of analog-to-digital conversions; and

means for selectively connecting the first plates of said first and second capacitors solely to each other during each pulse of said second train and disconnecting them from each other at least at times their second plates are connected to separate ones of the first and second output connection of said analog-to-digital converter.

11. A differential delta-sigma modulator as set forth in claim 10 wherein said means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second terminals only during each pulse in said second train essentially consists of:

means for selectively connecting the second plates of said first and second capacitors to said first and second terminals, respectively, only during each pulse of said second train in said first portions of analog-to-digital conversions; and

means for selectively connecting the second plates of said first and second capacitors to said second and first terminals, respectively, only during each pulse of said second train in said second portions of analog-to-digital conversions.

12. A differential delta-sigma modulator as set forth in claim 10 wherein said means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second terminals only during each pulse in said second train is of a type performing a single-bit multiplication of first input signal received between said first and second terminals by a second input signal.

13. A differential delta-signal modulator for performing analog-to-digital conversions each having respective first and second portions of similar duration, said differential detla-sigma modulator comprising:

first and second input terminals;

a first capacitor having respective first and second and second plates;

a second capacitor having respective first and second plates;

a third capacitor having respective first and second plates;

a fourth capacitor having respective first and second plates;

a differential amplifier having first and second output connections and having first and second input connections that are respectively inverting and non-inverting input connections insofar as said first output connection is concerned and are respectively non-inverting and inverting input connections insofar as said second output connection is concerned;

an analog-to-digital converter for resolving a differential voltage supplied thereto from between the first plates of said third and fourth capacitors, thereby to generate a single-bit output signal supplied in push-pull at first and second output connections thereof;

means for generating in staggered phase relationship a first train of pulses, a second train of pulses and a third train of pulses, pulses of which said trains occurs cyclically in order of their train number and do not overlap;

means for selectively connecting the first plates of said first and second capacitors to a common-mode potential only during each pulse of said first train;

means for selectively connecting the first plates of said first and second capacitors to the first and second input connections of said differential amplifier, respectively, only during each pulse of said third train;

means for selectively connecting said second plates of said first and second capacitors to separate ones of the first and second output connections of said analog-to-digital converter only during intervals between pulses in said second train including times when pulses appear in said first traain and times when pulses appear in said third train, connection being one way during said first portions of analog-to-digital conversions and being the other way during said second portions of analog-to-digital conversions;

means for selectively connecting the first plates of said first and second capacitors solely to each other during each pulse of said second train and disconnecting them from each other at least at times their second plates are connected to separate ones of the first and second output connections of said analog-to-digital converter;

means for selectively connecting the first and second plates of said third capacitor to the first output connection and first input connection of said differential amplifier, respectively, only during said first portions of analog-to-digital conversions;

means for selectively connecting the first and second plates of said third capacitor to the second output connection and second input connection of said differential amplifier, respectively, only during said second portions of analog-to-digital conversions;

means for selectively connecting the first and second plates of said fourth capacitor to the second output connection and first input connection of said differential amplifier, respectively, only during said first portions of analog-to-digital conversions;

means for selectively connecting said fourth capacitor from the first output connection of said differential amplifier to its first input connection only during said second portions of analog-to-digital conversions; and

means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second terminals only during each pulse of said second train in said first portions of analog-to-digital conversions.

14. A differential delta-sigma modulator as set forth in claim 13 wherein said means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second terminals only during each pulse in said second train essentially consists of:

means for selectively connecting the second plates of said first and second capacitors to said first and second terminals, respectively, only during each pulse of said second train in said first portions of analog-to-digital conversions; and

means for selectively connecting the second plates of said first and second capacitors to said second and first terminals, respectively, only during each pulse of said second train in said second portions of analog-to-digital conversions.

15. A differential delta-sigma modulator as set forth in claim 13 wherein said means for selectively connecting the second plates of said first and second capacitors to separate ones of said first and second terminals only during each pulse in said second train is of a type performing a single-bit multiplication of first input signal received between said first and second terminals by a second input signal.

16. A method of applying the difference between first and second input voltages to a differential delta-sigma modulator via first and second input capacitors in a switched-capacitance network, to remove the need for balancing said first and second input voltages, said method cyclically employing the following three steps in listed order;

charging the first and second capacitors in accordance with a previous single-bit output signal from said differential delta-sigma modulator;

connecting the first and second capacitors in series to receive the difference between the first and second input voltages for said differential delta-sigma modulator; and

discharging said first and second capacitors from first plates thereof to respective terminals of a differential input circuit of said differential delta-sigma modulator while second plates of said first and second capacitors are driven in accordance with said previous single-bit output signal from said differential delta-sigma modulator.

17. A method of applying the difference between first and second input voltages to a differential delta-sigma modulator via first and second input capacitors in a switched-capacitance network, to remove the need for balancing said first and second input voltages, said method cyclically employing the following three steps in listed order:

differentially charging the first and second capacitors in accordance with a previous single-bit output signal from said differential delta-sigma modulator;

connecting the first and second capacitors in series to receive the difference between the first and second input voltages for said differential delta-sigma modulator; and

discharging said first and second capacitors from first plates thereof to respective terminals of a differential input circuit of said differential delta-sigma modulator while second plates of said first and second capacitors are differentially driven in accordance with said previous single-bit output signal from said differential delta-sigma modulator.

18. A method as set forth in claim 17 wherein the step of connecting the first and second capacitors in series includes the substeps of

applying said first and second input voltages to separate ones of the second plates of said first and second capacitors;

and

connecting the first plates of said first and second capacitors to each other at a node free to float in potential as determined by the first and second input voltages applied to the second plates of said first and second capacitors and the charges stored between the plates of each of said first and second capacitors.