Data processor having integrated circuit memory refresh

• US 4,896,260 A
• Filed: 04/24/1989
• Issued: 01/23/1990
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US07/343,112
• Time in Patent Office: 274 Days
• Field of Search: 364/200, 364/900
• US Class Current: 711/106
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/12 : using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry.

Claims

1. An integrated circuit digital processing system comprising:

an integrated circuit dynamic memory storing digital data;

an integrated circuit digital processor coupled to the integrated circuit dynamic memory and processing the digital data stored by said integrated circuit dynamic memory;

an integrated circuit control circuit periodically generating a refresh signal to command refresh of the digital data stored by said integrated circuit dynamic memory; and

an integrated circuit refresh circuit coupled to said integrated circuit dynamic memory and coupled to said integrated circuit control circuit and refreshing the digital data stored by said integrated circuit dynamic memory in response to the refresh signal without conflict with the processing of the digital data by said integrated circuit digital processor.

2. An integrated circuit digital processing system as set forth in claim 1, wherein said integrated circuit digital processor is a stored program integrated circuit digital processor for processing the digital data stored by said integrated circuit dynamic memory in response to a stored program, wherein said integrated circuit digital processor includes an integrated circuit read only memory for storing a program having a plurality of computer instructions, wherein said integrated circuit dynamic memory includes an integrated circuit dynamic MOS-FET shift register memory for storing the digital data, wherein said integrated circuit refresh circuit includes a shift register recirculation circuit for refreshing the digital data stored by said integrated circuit dynamic MOS-FET shift register memory by recirculating the digital data in response to a refresh signal, wherein said integrated circuit digital processor includes an instruction execution circuit for processing the digital data stored by said integrated circuit dynamic MOS-FET shift register memory by executing the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit control circuit includes a micro-operation circuit for periodically generating the refresh signal at a particular micro-operation word time to command the integrated circuit refresh circuit to refresh said integrated circuit dynamic MOS-FET shift register memory without conflict with the processing of the digital data by said integrated circuit digital processor at other micro-operation word times, and wherein said integrated circuit control circuit includes a disable circuit for discontinuing processing of the digital data stored by said dynamic memory during the particular micro-operation word time to refresh said dynamic MOS-FET shift register memory in response to the refresh signal generated by said integrated circuit control circuit.

3. An integrated circuit digital processing system as set forth in claim 1, wherein said integrated circuit digital processor is a stored program integrated circuit digital processor for processing the digital data stored by said integrated circuit dynamic memory under control of a stored program, wherein said integrated circuit dynamic memory includes an integrated circuit dynamic random access memory for storing the digital data, wherein said integrated circuit dynamic random access memory includes memory locations for storing a program having a plurality of computer instructions, wherein said integrated circuit refresh circuit includes a random access memory refresh circuit for refreshing the digital data and the computer instructions stored by said integrated circuit dynamic random access memory, wherein said integrated circuit digital processor includes an instruction execution circuit for processing the digital data stored by said integrated circuit dynamic random access memory by executing the computer instructions stored by said integrated circuit random access memory, wherein said integrated circuit control circuit is arranged to periodically generate the refresh signal to command the integrated circuit refresh circuit to refresh said integrated circuit dynamic random access memory without conflict with the processing of the digital data by said integrated circuit digital processor, and wherein said integrated circuit control circuit includes a disable circuit for inhibiting processing of the digital data stored by said dynamic memory during the particular micro-operation word time that said dynamic memory is refreshed in response to the refresh signal generated by said integrated circuit control circuit.

8. An integrated circuit digital processing system as set forth in claim 1, further comprising:

an address register storing a memory address and

an address decoder generating a plurality of decoded address signals in response to the memory address stored by said address register; and

wherein said integrated circuit dynamic memory includes a plurality of integrated circuit dynamic memory chips storing the digital data, wherein each of said plurality of integrated circuit dynamic memory chips is selected by at least one of the plurality of decoded address signals generated by said address decoder, wherein said integrated circuit refresh circuit is coupled to refresh the digital data stored by said plurality of integrated circuit dynamic memory chips included in said integrated circuit dynamic memory in response to the refresh signal, wherein said integrated circuit digital processor is coupled to process the digital data stored by a selected integrated circuit dynamic memory chip included in said integrated circuit dynamic memory in response to a decoded address signal generated by said address decoder, and wherein said integrated circuit control circuit periodically generates the refresh signal to command the integrated circuit refresh circuit to refresh digital data stored by said plurality of integrated circuit dynamic memory chips included in said integrated circuit dynamic memory, the digital data being refreshed without conflict with the processing of the digital data by said integrated circuit digital processor.

4. An integrated circuit digital processing system comprising:

an integrated circuit dynamic memory storing digital data;

an integrated circuit digital processor coupled to the integrated circuit dynamic memory and processing the digital data stored by said integrated circuit dynamic memory;

an integrated circuit control circuit periodically generating a refresh signal to command refresh of the digital data stored by said integrated circuit dynamic memory;

an integrated circuit refresh circuit coupled to said integrated circuit dynamic memory and coupled to said integrated circuit control circuit and refreshing the digital data stored by said integrated circuit dynamic memory in response to the refresh signal without conflict with the processing of the digital data by said integrated circuit digital processor; and

a disable circuit coupled to said integrated circuit digital processor and to said integrated circuit control circuit to disable the processing by said integrated circuit digital processor of the digital data stored by said integrated circuit dynamic memory during refreshing of said dynamic memory in response to the refresh signal.

5. A digital processing system as set forth in claim 4, further comprising an integrated circuit program memory storing a program, and wherein said integrated circuit digital processor includes a program controlled circuit processing digital data stored by said integrated circuit dynamic memory in response to the program stored by said integrated circuit program memory.

7. A digital processing system as set forth in claim 4, wherein said integrated circuit dynamic memory includes an integrated circuit dynamic program memory storing a program, and wherein said integrated circuit digital processor includes a program controlled circuit processing digital data stored by said integrated circuit dynamic memory in response to the program stored by said integrated circuit dynamic program memory.

6. An integrated circuit digital processing system comprising:

an integrated circuit read only memory storing a program;

an integrated circuit dynamic memory storing digital data;

an integrated circuit digital processor coupled to the data integrated circuit read only memory and to the integrated circuit dynamic memory and processing digital data stored by said integrated circuit dynamic memory in response to the program stored by said integrated circuit read only memory;

an integrated circuit control circuit periodically generating a refresh signal to command refresh of the digital data stored by said integrated circuit dynamic memory;

an integrated circuit refresh circuit coupled to said integrated circuit dynamic memory and coupled to said integrated circuit control circuit and refreshing the digital data stored by said integrated circuit dynamic memory in response to the refresh signal without conflict with the processing of the digital data by said integrated circuit digital processor; and

a disable circuit coupled to said integrated circuit digital processor and to said integrated circuit control circuit to disable the processing by said integrated circuit digital processor of the digital data stored by said dynamic memory during refreshing of said dynamic memory in response to the refresh signal.

9. An integrated circuit digital processing system comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits;

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of a selected state among the plurality of more significant bits in the memory address;

an integrated circuit dynamic memory coupled to said integrated circuit memory address detector and storing digital data in response to the address detector signal;

an integrated circuit digital processor coupled to the an integrated circuit dynamic memory and processing the digital data stored by said integrated circuit dynamic memory;

an integrated circuit control circuit periodically generating a refresh signal to command refresh of the digital data stored by said integrated circuit dynamic memory; and

an integrated circuit refresh circuit coupled to said integrated circuit dynamic memory and coupled to said integrated circuit control circuit and refreshing the digital data stored by said integrated circuit dynamic memory in response to the refresh signal without conflict with the processing of the digital data by said integrated circuit digital processor.

10. An integrated circuit digital computer comprising:

an integrated circuit dynamic memory storing computer instructions and computer operands;

an integrated circuit refresh circuit coupled to refresh the computer instructions and computer operands stored by said integrated circuit dynamic memory in response to a refresh signal;

integrated circuit processing logic coupled to process the computer operands stored by said integrated circuit dynamic memory in response to the computer instructions stored by said integrated circuit dynamic memory; and

an integrated circuit control circuit coupled to periodically generate the refresh signal to command the integrated circuit refresh circuit to refresh said integrated circuit dynamic memory during a time interval that does not conflict with the processing of the computer operands by said integrated circuit processing logic.

11. A computer as set forth in claim 10, further comprising:

an address register storing a memory address; and

an address decoder coupled to the address register and generating a plurality of decoded address signals in response to the memory address stored by said address register; and

wherein said integrated circuit dynamic memory includes a plurality of integrated circuit dynamic memory chips storing the computer instructions and computer operands, wherein each of said plurality of integrated circuit dynamic memory chips is selected by at least one of the plurality of decoded address signals generated by said address decoder, wherein said integrated circuit refresh circuit is coupled to refresh the computer instructions and computer operands stored by said plurality of integrated circuit dynamic memory chips included in said integrated circuit dynamic memory in response to the refresh signal, wherein said integrated circuit processing logic is coupled to receive from the dynamic memory and process the computer instructions stored by a selected integrated circuit dynamic memory chip included in said integrated circuit dynamic memory in response to a decoded address signal generated by said address decoder, and wherein said integrated circuit control circuit periodically generates the refresh signal to refresh said plurality of integrated circuit dynamic memory chips included in said integrated circuit dynamic memory without conflict with the receiving of the computer operands by said integrated circuit processing logic.

12. A digital computer as set forth in claim 10, further comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits; and

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of a predetermined state among the plurality of more significant bits in the memory address; and

wherein said integrated circuit dynamic memory is coupled to receive the memory address detector signal and to store the computer instructions and the computer operands in response thereto.

13. A digital computer system comprising:

an integrated circuit dynamic memory storing digital information which includes computer instructions and computer operands;

an integrated circuit instruction execution control circuit generating a sequence of instruction execution control signals to control execution of a computer instruction stored by said integrated circuit dynamic memory;

an integrated circuit processor coupled to the instruction execution control circuit and processing the computer operands stored by said integrated circuit dynamic memory in response to the sequence of instruction execution control signals generated by said integrated circuit instruction execution control circuit;

a refresh control circuit generating a refresh control signal after completion of the sequence of instruction execution control signals generated by said integrated circuit instruction execution control circuit; and

a refresh execution circuit coupled to receive the refresh control signal and to refresh the digital information stored by said integrated circuit dynamic memory in response thereto.

14. A digital computer system comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits;

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of a selected state among the plurality of more significant bits in the memory address;

an integrated circuit dynamic memory coupled to said integrated circuit memory address detector and storing digital information which includes computer instructions and computer operands in response to the memory address detector signal;

an integrated circuit instruction execution control circuit generating a sequence of instruction execution control signals to control execution of a computer instruction stored by said integrated circuit dynamic memory;

an integrated circuit processor coupled to the instruction execution control circuit and to the integrated circuit dynamic memory and processing the computer operands stored by the integrated circuit dynamic memory in response to the sequence of instruction execution control signals generated by said integrated circuit instruction execution control circuit;

a refresh control circuit generating a refresh control signal after completion of the sequence of instruction execution control signals generated by said integrated circuit instruction execution control circuit; and

a refresh execution circuit coupled to receive the refresh control signal and to refresh the digital information stored by said integrated circuit dynamic memory in response thereto.

15. A stored program digital processor comprising:

a dynamic memory storing digital instructions;

a control circuit including an instruction execution control circuit generating a sequence of instruction execution control signals controlling execution of instructions and a refresh control circuit generating a refresh signal following a sequence of instruction execution control signals generated by said instruction execution control circuit;

an instruction execution circuit coupled to receive and execute instructions stored by said dynamic memory in response to the sequence of instruction execution control signals generated by said instruction execution control circuit; and

a refresh circuit coupled to refresh said dynamic memory in response to the refresh signal generated by said refresh control circuit.

16. A stored program computer system comprising:

a dynamic memory storing a program having a plurality of computer instructions;

an instruction execution circuit coupled to execute computer instructions stored by said dynamic memory; and

a refresh circuit coupled to refresh said dynamic memory without conflicting with execution by said instruction execution circuit of a computer instruction stored by the dynamic memory.

23. A computer system as set forth in claim 16, wherein said dynamic memory is a dynamic random access memory and wherein said system further comprises:

a memory address register storing a memory address having a plurality of bits; and

a memory address detector coupled to the address register and generating a memory address detector signal in response to detection of a selected state among a predetermined plurality of the bits in the stored memory address;

wherein said dynamic random access memory is coupled to receive the memory address detector signal and stores the computer instructions in response thereto; and

wherein said instruction execution circuit is coupled to the dynamic random access memory and executes the computer instructions stored by said dynamic random access memory by executing the computer instructions stored by said dynamic random access memory.

24. A computer system as set forth in claim 16, wherein said dynamic memory stores computer operands;

wherein said dynamic memory is a dynamic random access memory;

wherein said system further comprises a read only memory storing computer instructions; and

wherein said instruction execution circuit includes a processing circuit coupled to the dynamic memory and to the read only memory, the processing circuit processing the computer operands stored by said dynamic random access memory by executing the computer instructions stored by said dynamic random access memory and by said read only memory.

17. A stored program computer system comprising:

an address register storing a memory address;

an address decoder coupled to the address register and generating a plurality of decoded address signals in response to the memory address stored by said address register;

a dynamic random access memory coupled to said address decoder and storing a program having a plurality of computer instructions and storing a plurality of computer operands, wherein said dynamic random access memory includes a plurality of integrated circuit dynamic random access memory chips storing the computer instructions and the computer operands, wherein each of said plurality of integrated circuit dynamic random access memory chips is selected by at least one of the plurality of decoded address signals generated by said address decoder;

a refresh circuit coupled to refresh the digital data stored by said plurality of dynamic random access memory chips included in said dynamic random access memory without conflicting with execution of a computer instruction by said instruction execution circuit;

an instruction execution circuit coupled to execute the computer instructions stored by a selected dynamic random access memory chip included in said dynamic random access memory in response to a decoded address signal generated by said address decoder to process the computer operands stored by a selected dynamic random access memory chip included in said dynamic random access memory in response to a decoded address signal generated by said address decoder; and

a refresh circuit coupled to said dynamic random access memory and periodically refreshing said plurality of dynamic random access memory chips included in said dynamic random access memory without conflicting with execution by said instruction execution circuit of a computer instruction stored by the dynamic memory.

18. A stored program computer system comprising:

a dynamic random access memory storing a program having a plurality of computer instructions;

a control circuit generating micro-operation signals, said control circuit including

(1) a first micro-operation circuit generating instruction execution micro-operation signals and

(2) a second micro-operation circuit generating a refresh micor-operation signal;

an instruction execution circuit coupled to said first micro-operation circuit and executing computer instructions stored by said dynamic random access memory in response to the instruction execution micro-operation signals;

a refresh circuit coupled to said second micro-operation circuit and refreshing said dynamic random access memory in response to the refresh micro-operation signal without conflicting with execution of a computer instruction by said instruction execution circuit.

19. A stored program computer system comprising:

an integrated circuit memory address register storing a memory address;

an integrated circuit memory address detector generating a memory address detector signal in response to detection of a selected state among a selected plurality of the bits in the memory address;

a dynamic memory coupled to receive the memory address detector signal and to store a plurality of computer instructions in response thereto;

an instruction execution circuit coupled to execute computer instructions stored by said dynamic memory; and

a refresh circuit coupled to refresh said dynamic memory without conflicting with execution by said instruction execution circuit of a computer instruction stored by the dynamic memory.

20. A stored program computer system comprising:

a dynamic random access memory storing a program having a plurality of computer instructions and storing computer operands;

an instruction execution circuit coupled to the dynamic random access memory and processing the computer operands stored by said dynamic random access memory by executing the computer instructions stored by said dynamic random access memory; and

a refresh circuit coupled to refresh said dynamic random access memory without conflicting with execution by said instruction execution circuit of a computer instruction stored by the dynamic memory.

21. A stored program computer system comprising;

a dynamic memory storing a program having a plurality of computer instructions;

an instruction execution circuit coupled to execute computer instructions stored by said dynamic memory; and

a refresh circuit coupled to refresh said dynamic memory without conflicting with execution of a computer instruction by said instruction execution circuit by disabling execution of the computer instructions stored by said dynamic memory during refreshing of said dynamic memory.

22. A stored program computer system comprising:

a dynamic random access memory storing a program having a plurality of computer instructions;

an instruction execution circuit coupled to execute computer instructions stored by said dynamic memory; and

a refresh circuit coupled to refresh said dynamic random access memory without conflicting with execution of a computer instruction by said instruction execution circuit by inhibiting execution of the computer instructions stored by said dynamic random access memory during refreshing of said dynamic random access memory.

25. A digital processor system comprising:

an oscillator circuit generating an oscillator signal;

a clock gating flip-flop coupled to receive the oscillator signal and generating a clock gating signal in response thereto;

a gate coupled to receive the oscillator signal and the clock gating signal, the gate generating a gated clock signal in response to the oscillator signal generated by said oscillator circuit and the clock gating signal generated by said clock gating flip-flop; and

a digital processor receiving the gated clock signal and processing digital data in response to the gated clock signal.

26. A digital processing system as set forth in claim 25, wherein said digital processor system is a digital computer system, wherein said oscillator circuit is an 8 MHz oscillator circuit generating the oscillator signal as an 8 MHz oscillator signal, wherein said clock gating flip-flop is JK flip-flop generating the clock gating signal as a toggled clock gating signal in response to being clocked by the 8 MHz oscillator signal generated by said oscillator circuit, wherein said gate is a NAND gate generating the gated clock signal as a NANDed gated clock signal by NANDing the 8 MHz oscillator signal generated by said oscillator circuit and the toggled clock gating signal generated by said clock gating flip-flop, and wherein said digital processor is an integrated circuit stored program digital computer processing the digital data in response to the gated clock signal generated by said gate;

wherein said integrated circuit stored program digital computer includes;

(a) an integrated circuit read only memory storing a program having a plurality of computer instructions,

(b) an integrated circuit MOS-FET shift register dynamic memory storing computer operands,

(c) integrated circuit processing logic receiving from the dynamic memory and processing the computer operands stored by said dynamic memory in response to the stored program computer instructions stored by said integrated circuit read only memory, and

(d) an integrated circuit refresh circuit refreshing said dynamic memory without contention with the processing of the computer operands by said integrated circuit processing logic.

27. A processor system as set forth in claim 25, wherein said gate includes an asymmetrical gate circuit generating the gated clock signal as an asymmetrical gated clock signal in response to the oscillator signal generated by said oscillator circuit and the clock gating signal generated by said clock gating flip-flop.

28. An integrated circuit digital processor comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits;

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of at least one selected state of, but not all states of, the plurality of more significant bits in the memory address;

an integrated circuit random access memory coupled to receive the memory address detector signal and to store digital data in response thereto; and

an integrated circuit digital processor coupled to the integrated circuit random access memory and processing the digital data stored by said integrated circuit random access memory.

29. An integrated circuit digital processor comprising;

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits;

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of at least one selected state of, but not all states of, the plurality of more significant bits in the memory address;

an integrated circuit address decoder coupled to said integrated circuit memory address register and generating a plurality of decoded address signals in response to the memory address stored by said integrated circuit memory address register;

an integrated circuit random access memory coupled to receive the memory address detector signal and to store digital data in response thereto;

said integrated random access memory including a plurality of integrated circuit random access memory chips storing the digital data;

wherein each of said plurality of integrated circuit random access memory chips is selected by at least one of the plurality of decoded address signals generated by said address decoder; and

an integrated circuit digital processor coupled to the integrated circuit random access memory and processing the digital data stored by a selected integrated circuit random access memory chip included in said integrated circuit random access memory in response to a decoded address signal generated by said address decoder.

30. An integrated circuit digital processor comprising:

an integrated circuit read only memory storing computer instructions;

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits;

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of at least one selected state of, but not all states of, the plurality of more significant bits in the memory address;

an integrated circuit random access memory coupled to receive the memory address detector signal and store digital data in response thereto; and

an integrated circuit digital processor coupled to the integrated circuit read only memory and to the integrated circuit random access memory and processing the digital data stored by said integrated circuit random access memory in response to the instructions stored by said integrated circuit read only memory.

31. An integrated circuit digital processor comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits;

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of at least one selected state of, but not all states of, the plurality of more significant bits in the memory address;

an integrated circuit random access memory coupled to receive the memory address detector signal and store digital data in response thereto;

an integrated circuit digital processor coupled to the integrated circuit random access memory and processing the digital data stored by said integrated circuit random access memory; and

an integrated circuit refresh circuit coupled to the random access memory and to the integrated circuit digital processor and refreshing the digital data stored therein in response to the processing of the digital data stored by said integrated circuit random access memory.

32. An integrated circuit digital processor comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits;

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of at least one selected state of, but not all states of, the plurality of more significant bits in the memory address;

an integrated circuit random access memory coupled to receive the memory address detector signal and store digital data in response thereto; and

an integrated circuit digital processor coupled to the integrated circuit random access memory and processing the digital data stored by said integrated circuit random access memory; and

an integrated circuit refresh circuit coupled to the integrated circuit random access memory and refreshing the digital data stored therein in response to the processing of the digital data stored by said integrated circuit random access memory to prevent conflict with the processing of the digital data by said integrated circuit digital processor.

44. A digital computer as set forth in claim 32, further comprising:

an address register storing a memory address; and

an address decoder generating a plurality of decoded address signals in response to the memory address stored by said address register; and

wherein said dynamic integrated circuit memory includes a plurality of dynamic integrated circuit memory chips;

wherein each of said plurality of dynamic integrated circuit memory chips is selected by at least one of the plurality of decoded address signals generated by said address decoder;

wherein said integrated circuit execution logic executes the computer instructions stored by a selected dynamic integrated circuit memory chip included in said dynamic integrated circuit memory in response to a decoded address signal generated by said address decoder, and wherein said integrated circuit refresh circuit refreshes the computer instructions and computer operands stored by said plurality of dynamic integrated circuit memory chips in response to execution of a stored computer instruction.

33. A stored program digital processor comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits;

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of at least one predetermined state of, but not all states of, the plurality of more significant bits in the memory address;

an integrated circuit random access memory coupled to receive the memory address detector signal, the memory storing a program having a plurality of computer instructions and storing computer operands in response to receipt of the memory address detector signal generated by said integrated circuit memory address detector; and

an integrated circuit digital processor coupled to the random access memory, the digital processor processing the computer operands stored by said integrated circuit random access memory in response to the computer instructions stored by said integrated circuit random access memory.

34. A stored program digital computer comprising:

an integrated circuit dynamic memory storing a computer program having a plurality of computer instructions and storing computer operands;

integrated circuit execution logic coupled to the dynamic memory and executing computer instructions stored by said integrated circuit dynamic memory, said integrated circuit execution logic processing computer operands stored by said integrated circuit dynamic memory in response to execution of the stored computer instructions, said integrated circuit execution logic including an integrated circuit sequential logic circuit generating a sequence of control signals in response to execution of a stored computer instruction; and

an integrated circuit refresh circuit coupled to the dynamic memory, the refresh circuit refreshing the computer instructions and the computer operands stored by said integrated circuit dynamic memory in response to at least one of the sequence of control signals generated by said integrated circuit sequential logic circuit.

35. A stored program digital computer as set forth in claim 34, wherein said integrated circuit dynamic memory includes a MOSFET integrated circuit shift register memory storing the computer operands.

36. A stored program digital computer as set forth in claim 34, wherein said stored program digital computer is an all integrated circuit stored program digital computer implemented on a plurality of integrated circuit chips.

37. A digital computer as set forth in claim 34, wherein said integrated circuit dynamic memory is an integrated circuit dynamic random access memory.

38. A digital computer as set forth in claim 34, wherein said integrated circuit dynamic memory is an integrated circuit dynamic random access memory;

and wherein the refresh circuit responds to the at least one of the sequence of control signals by refreshing the dynamic memory at a time that does not conflict with reading of operands from the dynamic memory for processing by the execution logic.

39. A digital computer as set forth in claim 34, wherein said integrated circuit dynamic memory is an integrated circuit dynamic random access memory;

and wherein said integrated circuit refresh circuit is coupled for refreshing the computer instructions and the computer operands stored by said integrated circuit dynamic random access memory at a time period during which said integrated circuit execution logic is not reading the computer operands from the dynamic memory.

40. A stored program digital computer comprising:

an integrated circuit dynamic random access memory storing a computer program having a plurality of computer instructions and storing computer operands;

integrated circuit execution logic coupled to the integrated circuit dynamic random access memory and executing computer instructions stored by said integrated circuit dynamic random access memory, the integrated circuit execution logic processing computer operands stored by said integrated circuit dynamic random access memory in response to execution of the stored computer instructions, the integrated circuit execution logic including an integrated circuit sequential logic circuit generating a sequence of control signals in response to execution of a stored computer instruction;

an integrated circuit refresh circuit coupled to the integrated circuit dynamic random access memory, the refresh circuit refreshing the computer instructions and the computer operands stored by said integrated circuit dynamic random access memory in response to at least one of the sequence of control signals generated by said integrated circuit sequential logic circuit; and

a disable circuit coupled to disable the processing of the computer operands by said integrated circuit execution logic during refresching of the computer instructions and the computer operands stored by said integrated circuit dynamic random access memory.

41. A stored program digital computer comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits; and

an integrated circuit memory address detector coupled to the memory address register and generating a memory address detector signal in response to detection of the plurality of more significant bits in the memory address;

a dynamic integrated circuit memory coupled to receive the detector signal and storing a computer program having a plurality of computer instructions and storing computer operands in response thereto;

integrated circuit execution logic coupled to the dynamic integrated circuit memory and executing computer instructions stored by said dynamic integrated circuit memory, the execution logic processing computer operands stored by said dynamic integrated circuit memory in response to the stored instructions, said integrated circuit execution logic including an integrated circuit sequential logic circuit generating a sequence of control signals in response to execution of a stored computer instruction; and

an integrated circuit refresh circuit coupled to the dynamic integrated circuit memory, the refresh circuit refreshing the computer instructions and the computer operands stored by said integrated circuit dynamic memory in response to at least one of the sequence of control signals generated by said integrated circuit sequential logic circuit.

42. An integrated circuit stored program digital computer comprising:

a dynamic integrated circuit memory storing a computer program having a plurality of computer instructions and storing a plurality of computer operands;

integrated circuit execution logic coupled to the dynamic integrated cirucit memory, the execution logic executing the computer instructions stored by said dynamic integrated circuit memory and processing the computer operands stored by said dynamic integrated circuit memory in response to said instructions; and

an integrated circuit refresh circuit coupled to the dynamic integrated circuit memory and to the execution logic, the refresh circuit refreshing the computer instructions and the computer operands stored by said dynamic integrated circuit memory in response to execution by the execution logic of at least one stored computer instruction.

43. A stored program digital computer according to claim 42 wherein said dynamic integrated circuit memory includes an integrated circuit register requiring a refresh signal to be provided at a rate at least as high as a minimum refresh rate to preserve the computer program and the computer operands stored therein;

wherein the instruction execution rate is at least as high as the minimum refresh rate; and

wherein the refresh signal is generated in response to execution of a computer instruction stored by said dynamic integrated circuit memory.

45. A digital computer as set forth in claim 42, further comprising:

an integrated circuit memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits; and

an integrated circuit memory address detector coupled to generate a memory address detector signal in response to detection of the plurality of more significant bits in the memory address; and

wherein said dynamic integrated circuit memory stores the computer instructions and the computer operands in response to the memory address detector signal.

46. A digital computer as set forth in claim 42, wherein said dynamic integrated circuit memory is a dynamic integrated circuit random access memory.

47. A digital computer as set forth in claim 42, wherein said dynamic integrated circuit memory is a dynamic integrated circuit random access memory;

wherein said refresh circuit refreshes the computer instructions and the computer operands stored by said dynamic integrated circuit random access memory in response to execution of a stored computer instruction without conflict with the processing of the computer operands by said integrated circuit execution logic.

48. A digital computer as set forth in claim 42, wherein said dynamic integrated circuit memory is a dynamic integrated circuit random access memory;

wherein said integrated circuit refresh circuit refreshes the computer instructions and the computer operands stored by said dynamic integrated circuit random access memory in response to execution of a stored computer instruction at a time in which said integrated circuit execution logic is not reading the computer operands from the dynamic memory.

49. A digital computer as set forth in claim 42, wherein said dynamic integrated circuit memory is a dynamic integrated circuit access memory;

wherein said computer further includes in integrated circuit sequential logic circuit generating a sequence of control signals in response to execution of a stored computer instruction;

wherein said integrated circuit execution logic includes control signal responsive execution logic executing the computer instructions stored by said dynamic integrated circuit random access memory to process the computer operands stored by said dynamic integrated circuit random access memory in response to the sequence of control signals generated by said integrated circuit sequential logic circuit; and

wherein said integrated circuit refresh circuit refreshes the computer instructions and the computer operands stored by said dynamic integrated circuit random access memory in response to at least one of the instruction execution responsive control signals generated by said integrated circuit sequential logic circuit.

50. An integrated circuit stored program digital computer system comprising:

a memory address register storing a memory address having a plurality of less significant bits and having a plurality of more significant bits; and

a memory address detector coupled to said memory address register and generating a memory address detector signal in response to detection of the plurality of more significant bits in the memory address;

a dynamic integrated circuit random access memory coupled to said memory address detector and storing a computer program having a plurality of computer instructions and storing a plurality of computer operands in response to the memory address detector signal.

integrated circuit execution logic coupled to the dynamic integrated circuit random access memory, the execution logic executing the computer instructions stored by said dynamic integrated circuit random access memory and processing the computer operands stored by said dynamic integrated circuit memory in response to said instructions; and

an integrated circuit refresh circuit coupled to the dynamic integrated circuit random access memory and to the execution logic, the refresh circuit refreshing the computer instructions and the computer operands stored by said dynamic integrated circuit random access memory in reponse to execution by the execution logic of at least one stored computer instruction.

51. A data processor system comprising:

an integrated circuit dynamic memory storing computer operands, the dynamic memory including a refresh circuit refreshing data stored therein in response to a memory refresh signal;

an integrated circuit read only memory storing computer instructions and computer operands; and

integrated circuit execution logic coupled to the dynamic memory and to the read only memory and executing the computer instructions stored by said read only memory, said integrated circuit execution logic including;

(a) a first processing logic circuit coupled to the read only memory and transferring to a computer instruction stored by said read only memory at an address indicated by an instruction address operand stored by said read only memory in response to execution of a multiple-byte transfer computer instruction stored by said read only memory,

(b) a second processing logic circuit coupled to the dynamic memory and to the read only memory and transferring to a computer instruction stored by said read only memory at an address indicated by an instruction address operand stored by said dynamic memory in response to execution of a single-byte transfer computer instruction stored by said read only memory, and

(c) a refresh circuit generating the memory refresh signal in response to execution of at least one of the computer instructions stored by said read only memory.

52. An integrated circuit stored program computer comprising:

an integrated circuit dynamic memory storing a program of computer instructions and storing computer operands;

integrated circuit execution logic coupled to the dynamic memory and executing the computer instructions stored by said integrated circuit dynamic memory, said integrated circuit execution logic including a processing logic circuit processing the computer operands stored by said dynamic memory in response to execution of at least one of the computer instructions stored by said integrated circuit dynamic memory; and

a refresh circuit coupled to the dynamic memory and to the execution logic and refreshing the computer instructions and the computer operands stored by said integrated circuit dynamic memory in response to execution by the execution logic of at least one of the computer instructions stored by said integrated circuit dynamic memory.

53. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory storing a program of computer instructions and storing computer operands, wherein said processing logic circuit includes a read only memory processing circuit coupled to the read only memory and processing a computer operand stored by said read only memory in response to a first type of computer instruction stored by said read only memory and a dynamic memory processing circuit processing a computer operand stored by said dynamic memory in response to a second type of computer instruction stored by said read only memory.

54. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory storing a program of computer instructions and storing computer operands, and wherein said integrated circuit execution logic includes a read only memory processing circuit coupled to the read only memory and processing the computer operands stored by said read only memory in response to execution of at least one of the computer instructions stored by said read only memory.

55. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory storing a program of computer instructions and storing computer operands, and wherein said integrated circuit execution logic includes a first arithmetic logic circuit performing an arithmetic operation with a computer operand stored by said read only memory in response to execution of a first type of arithmetic computer instruction stored by said read only memory and a second arithmetic logic circuit performing an arithmetic operation with a computer operand stored by said dynamic memory in response to execution of a second type of arithmetic computer instruction stored by said read only memory.

56. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory storing a program of computer instructions and storing computer operands, and wherein said integrated circuit execution logic includes a first transfer logic circuit coupled to the read only memory and transferring to a computer instruction stored by said read only memory addressed by an instruction address operand stored by said read only memory in response to execution of a first type of transfer computer instruction stored by said read only memory and a second transfer logic circuit coupled to the read only memory and transferring to a computer instruction stored by said read only memory addressed by an instruction address operand stored by said dynamic memory in response to execution of a second type of transfer computer instruction stored by said read only memory.

57. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory coupled to the execution logic and storing a program of computer instructions and storing computer operands, and wherein said integrated circuit execution logic includes a first logic circuit performing a logical operation with a computer operand stored by said read only memory in response to execution of a first type of logical computer instruction stored by said read only memory and a second logic circuit performing a logical operation with a computer operand stored by said dynamic memory in response to execution of a second type of logical computer instruction stored by said read only memory.

58. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory coupled to the execution logic and storing a program of computer instructions and storing computer operands, and wherein said integrated circuit execution logic includes a first index logic circuit performing an index operation with an index computer operand stored by said read only memory in response to execution of a first type of index computer instruction stored by said read only memory and a second index logic circuit performing an index operation with an index computer operand stored by said dynamic memory in response to execution of a second type of index computer instruction stored by said read only memory.

59. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory coupled to the execution logic and storing a program of computer instructions and storing computer operands, and wherein said integrated circuit execution logic includes a first arithmetic logic circuit performing an arithmetic operation with a computer operand stored by said read only memory in response to execution of a multiple-byte arithmetic computer instruction stored by said read only memory and a second arithmetic logic circuit performing an arithmetic operation with a computer operand stored by said dynamic memory in response to execution of a single-byte arithmetic computer instruction stored by said read only memory.

60. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory coupled to the execution logic and storing a program of computer instructions and storing computer operands, and wherein said integrated circuit execution logic includes a first logic circuit performing a logical operation with a computer operand stored by said read only memory in response to execution of a multiple-byte logical computer instruction stored by said read only memory and a second logic circuit performing a logical operation with a computer operand stored by said dynamic memory in response to execution of a single-byte logical computer instruction stored by said read only memory.

61. An integrated circuit stored program computer as set forth in claim 52, wherein said integrated circuit dynamic memory includes a plurality of memory pages storing a plurality of pages of data containing computer instructions and computer operands, said integrated circuit stored program computer further comprising a paging circuit coupled to the execution logic and selecting at least one of the plurality of memory pages of said integrated circuit dynamic memory in response to execution by the execution logic of a computer instruction stored by said read only memory.

62. An integrated circuit stored program computer as set forth in claim 52, further comprising:

an integrated circuit read only memory storing a program of computer instructions;

a read only memory address circuit generating a read only memory address;

a read only memory accessing circuit coupled to the read only memory and to the read only memory address circuit, the read only memory accessing circuit accessing a computer instruction stored by said read only memory in response to the read only memory address generated by said read only memory address circuit;

a dynamic memory address circuit generating a dynamic memory address; and

a dynamic memory accessing circuit coupled to the dynamic memory and to the dynamic memory address circuit, the dynamic memory accessing circuit accessing a computer operand stored by said dynamic memory in response to the dynamic memory address generated by said dynamic memory address circuit, wherein the execution logic is coupled to receive and execute said accessed computer instruction stored by the read only memory and to receive and process said accessed operand stored by the dynamic memory, and wherein at least a part of the time for accessing a computer instruction stored by said read only memory is coincident with at least a part of the time for accessing a computer operand stored by said dynamic memory.

63. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory storing a program of computer instructions, an integrated circuit read only memory accessing circuit accessing a computer instruction stored by said read only memory, an integrated circuit dynamic memory accessing circuit accessing a computer operand stored by said dynamic memory, and an accessing control circuit controlling overlapping accessing of a computer instruction from said read only memory and a computer operand from said dynamic memory in response to a command from the execution logic.

64. An integrated circuit stored program computer as set forth in claim 52, wherein said integrated circuit execution logic includes a storing circuit storing a sixteen-bit computer instruction address in said dynamic memory in response to execution of an eight-bit computer instruction stored by said integrated circuit dynamic memory.

65. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory storing eight-bit computer instructions, wherein said dynamic memory includes at least one storing location storing a sixteen-bit computer operand, and wherein said processing logic circuit includes a sixteen bit processing logic circuit processing a sixteen-bit computer operand stored by said dynamic memory in response to execution of an eight-bit computer instruction stored by said read only memory.

66. An integrated circuit stored program computer as set forth in claim 52, further comprising an integrated circuit read only memory storing eight-bit computer instructions and storing sixteen-bit computer operands, and wherein said integrated circuit execution logic includes a loading circuit loading a sixteen-bit computer operand from said read only memory into said dynamic memory in response to execution of an eight-bit computer instruction stored by said read only memory.

69. A data processing system as set forth in claim 61, wherein said read only memory includes an instruction read only memory storing an eight-bit instruction, wherein said dynamic memory includes an operand dynamic memory storing sixteen-bit information in response to the refresh signal, and wherein said processing logic circuit includes a sixteen-bit processing logic circuit processing the sixteen-bit information stored by said operand dynamic memory in response to execution of an eight-bit instruction stored by said instruction read only memory.

67. A data processing system comprising:

an integrated circuit read only memory storing processor instructions;

an integrated circuit dynamic memory storing processed information in response to a memory refresh signal; and

an execution circuit coupled to the read only memory and to the dynamic memory and executing the instructions stored by said read only memory, said execution circuit including

(a) a processing logic circuit processing the information stored by said dynamic memory in response to execution of an instruction stored by said read only memory and

(b) a synchronization circuit generating the memory refresh signal in synchronization with and in response to execution of an instruction stored by said read only memory.

68. A data processing system as set forth in claim 67, wherein said processing logic circuit and said synchronization circuit are implemented on multiple integrated circuit chips.

71. A data processing system as set forth in claim 67, wherein said execution circuit includes:

a single byte accessing circuit accessing a single byte instruction stored by said read only memory;

a single byte execution circuit executing the single byte instruction accessed by said single byte accessing circuit;

a double byte accessing circuit accessing a double byte instruction stored by said read only memory;

a double byte execution circuit executing the double byte instruction accessed by said double byte accessing circuit;

a triple byte accessing circuit accessing a triple byte instruction stored by said read only memory; and

a triple byte execution circuit executing the triple byte instruction accessed by said triple byte accessing circuit.

72. A data processing system as set forth in claim 67, wherein said processing logic circuit includes a loading circuit loading digital information that is stored by said read only memory into said dynamic memory, said loading circuit including:

an instruction accessing circuit accessing a load instruction from said read only memory;

an operand accessing circuit accessing the stored digital information to be loaded from said read only memory in response to execution of the load insturction accessed from said read only memory by said instruction accessing circuit; and

a storing circuit storing the digital information accessed from said read only memory by said operand accessing circuit in said dynamic memory in response to execution of the load instruction accessed from said read only memory by said instruction accessing circuit.

73. A data processing system as set forth in claim 67, further comprising:

a display displaying information in response to a display refresh signal and

a display refresh circuit generating the display refresh signal in response to execution responsive processing of information stored by said dynamic memory.

70. A data processing system comprising:

an integrated circuit read only memory storing processor instructions;

an integrated circuit dynamic memory storing processed information in response to a memory refresh signal; and

an execution circuit coupled to the read only memory and to the dynamic memory and executing the instructions stored by said read only memory, said execution circuit including

(a) a micro-operation circuit generating a plurality of sequential micro-operations in response to an instruction stored by said read only memory,

(b) a processing logic circuit coupled to said dynamic memory and to said micro-operation circuit and processing the information stored by said dynamic memory by execution of the plurality of sequential micro-operations, and a synchronization circuit coupled to said said processing logic circuit and generating the memory refresh signal in synchronization with and in response to execution of an instruction responsive micro-operation.

74. A data processing system comprising:

an integrated circuit read only memory storing processor instructions;

an integrated circuit dynamic memory storing processed information in response to a memory refresh signal; and

an execution circuit coupled to the read only memory and to the dynamic memory and executing the instructions stored by said read only memory, said execution circuit including

(a) a micro-instruction logic circuit executing a plurality of micro-instructions in response to execution of an instruction stored by said read only memory,

(b) a processing logic circuit processing the information stored by said dynamic memory in response to execution of at least one of the instruction responsive micro-instructions generated by said micro-instruction logic circuit, and

(c) a synchronization circuit generating the memory refresh signal in response to execution of an instruction responsive micro-instruction.

75. A stored program computer comprising:

a main memory storing computer instructions;

an alterable integrated circuit memory storing alterable information in response to a refresh signal; and

an execution circuit coupled to the main memory and to the alterable integrated circuit memory, the execution circuit executing the computer instructions stored by said main memory, said execution circuit including

(a) a control circuit generating a sequence of control signals in response to execution of an instruction stored by said main memory wherein at least one of said sequence of control signals is the refresh signal, and

(b) a processing circuit processing the information stored by said alterable integrated circuit memory in response to at least one of the control signals in the sequence of control signals generated by said control circuit.

76. A computer as set forth in claim 75, wherein said alterable integrated circuit memory includes a register storing alterable information in response to the refresh signal.

77. A computer as set forth in claim 75, wherein said main memory is an integrated circuit read only memory storing the instructions in read only form and wherein said computer is a monolithic computer implemented on a plurality of integrated circuit chips.

78. A computer as set forth in claim 75, wherein said alterable memory includes:

an address register storing a memory address,

an integrated circuit random access memory storing the alterable information, and

an accessing circuit accessing alterable information stored by said integrated circuit random access memory at a location indicated by the memory address; and

wherein said processing circuit is coupled to receive and process the alterable information stored at the location indicated by the memory address.

79. A digital processing system comprising:

a dynamic memory storing digital data;

a digital processor coupled to the dynamic memory and communicating data with the dynamic memory;

a refresh circuit coupled to refresh the dynamic memory in response to a refresh signal; and

a control circuit coupled to communicate the refresh signal to the refresh circuit, the control circuit generating the refresh signal at selected intervals of time.

80. A digital processing system comprising:

a dynamic memory storing digital data;

a digital processor coupled to the dynamic memory and communicating data with the dynamic memory;

a refresh circuit coupled to refresh the dynamic memory in response to a refresh signal and to inhibit communication of data between the dynamic memory and the digital processor while the dynamic memory is being refreshed; and

a control circuit coupled to communicate the refresh signal to the refresh circuit, the control circuit generating the refresh signal at selected intervals of time.

81. A digital processing system comprising:

a dynamic memory storing digital data;

a processor coupled to communicate data between the processor and the dynamic memory; and

a refresh circuit coupled to refresh the dynamic memory with sufficient frequency to retain the data stored by the dynamic memory.

82. A digital processing system comprising:

a dynamic memory storing digital data;

a processor coupled to communicate data between the processor and the dynamic memory; and

a refresh circuit coupled to refresh the dynamic memory with sufficient frequency to retain the data stored by the dynamic memory and to inhibit communication of data between the dynamic memory and the processor while the dynamic memory is being refreshed.