Computer-controlled automatic logic design system for semiconductor integrated circuit devices

• US 4,896,272 A
• Filed: 03/30/1988
• Issued: 01/23/1990
• Est. Priority Date: 03/31/1987
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kurosawa, Yuichi
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Trans, V. N.
• Application Number:
  US07/175,288
• Time in Patent Office: 664 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/300, 364/521
• US Class Current: 716/102
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

There is disclosed a specific automatic logic design technique according to which, first, an initial logic circuit, which is automatically synthesized based on a "hardware description language" and using standard logic elements stored in advance as a library, is stored in a data storage unit. The logic circuit is displayed on a display device to permit an operator to assign, by using a block assignment unit, logic elements that must be grouped together as a single circuit block from the logic elements constituting the logic circuit so that the actual design conditions including restrictions for placement and wiring are satisfied. When the logic elements to be grouped together are assigned, they are combined as a circuit block before the logic circuit is subjected to automatic layout optimization processing. The logic circuit is rearranged to include the circuit block as a circuit section having a fixed internal circuit configuration. The circuit block is prohibited from being divided into several portions in the final automatic layout optimization processing.

Claims

1. A computer-controlled automatic logic design method comprising the steps of:

(a) storing in a data storage unit a logic circuit which is automatically synthesized based on a hardware description language by using standard logic elements which have been stored as a library;

(b) at least partially displaying the logic circuit on a display device to permit an operator to assign, among logic elements constituting the logic circuit, those which are necessary to be grouped together as a circuit block in order to satisfy actual design conditions including restrictions for placement and wiring;

(c) combining, when said logic elements to be grouped together are selected by an operator, these selected logic elements as a circuit block, before said logic circuit stored in said data storage unit is subjected to automatic layout optimization processing to thereby generate a circuit section having a fixed integral circuit arrangement which is prevented from being modified; and

(d) rearranging said logic circuit stored in said data storage unit including said circuit block in such a manner that the internal circuit arrangement of said circuit block is kept continuously unchanged, whereby said circuit block is prohibited from being divided into several portions in the automatic layout optimization processing.

2. The method according to claim 1, wherein said circuit block is defined, in said logic circuit, by detecting signal lines connecting logic elements included therein and logic elements located outside said circuit block and specifying detected signal lines.

3. The method according to claim 2, wherein said detected signal lines are identified as input/output terminals of said circuit block.

4. The method according to claim 3, wherein said detected signal lines are given code names for identification.

5. The method according to claim 4, wherein said circuit block is given a code name for identification.

6. A computer-controlled apparatus for automatic logic design using hardware description language, said apparatus comprising:

(a) data storage means for storing a logic circuit which is automatically synthesized based on the hardware description language using standard logic elements which have been stored as a library;

(b) display means for at least partially displaying said logic circuit;

(c) assignment means, manually operated by an operator, for assigning, among logic elements constituting said logic circuit, those required to be grouped together as a circuit block in order to satisfy actual design conditions including restrictions for placement and wiring;

(d) first processing means, connected to said assignment means, for combining, when said logic elements to be grouped together are selected by an operation using said assignment means, these selected logic elements as a circuit block, before said logic circuit stored in said data storage means is subjected to automatic layout optimization processing to thereby generate a circuit section having a fixed internal circuit arrangement which is prevented from being modified; and

(e) second processing means, connected to said first processing means, for rearranging said logic circuit stored in said data storage means including said circuit block in such a manner that the internal circuit arrangement of said circuit block is kept continuously unchanged, whereby said circuit block is prohibited from being divided into several portions in the automatic layout optimization processing.

7. The apparatus according to claim 6, wherein said first processing means detects signal lines connecting logic elements included in said circuit block and logic elements located outside said circuit block, and specifies detected signal lines, thereby defining a blocked region corresponding to said circuit block within said logic circuit.

8. The apparatus according to claim 7, wherein said first and second processing means are embedded in a central processing unit.

9. The apparatus according to claim 7, wherein said assignment means comprises at least one of a keyboard and a pointer.