Adjustable frequency signal generator system with incremental control

• US 4,896,337 A
• Filed: 04/08/1988
• Issued: 01/23/1990
• Est. Priority Date: 04/08/1988
• Status: Expired due to Term

• Current Assignee: Ampex Corporation (Delta Information Systems, Inc.)
• Original Assignee: Ampex Corporation (Delta Information Systems, Inc.)
• Inventors: Bushy, Edwin S. Jr.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US07/179,097
• Time in Patent Office: 655 Days
• Field of Search: 328/141, 328/155, 328/134, 328/72, 375/118, 375/119, 375/120, 370/108, 360/51, 377/52
• US Class Current: 375/371
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider

Abstract

An adjustable frequency signal generator is described which utilizes a stable fixed frequency oscillator in combination with an adjustable modulus frequency divider, to obtain a frequency divided output signal whose frequency may vary within a wide range, while maintaining spectral purity of a signal generated by the stable oscillator. In the preferred embodiment the modulus of the frequency divider is controlled by an up/down counter. The frequency of the frequency divided output signal is detected with respect to a reference signal frequency. When the detected output signal frequency is higher, the counter is incremented, thereby incrementing the modulus of the divider and decreasing the frequency of the output signal. Similarly, when the detected output signal frequency is lower than the reference signal frequency, the counter is decremented, whereby the modulus of the divider decreases and the output signal frequency increases. When the detected frequency is within predetermined limits of the reference signal frequency, the modulus is maintained constant. The rate of change of the output signal frequency is independent of any signal frequencies in the system and may be selected by selecting a desired clock rate for the up/down counter.

Claims

1. A system receiving and storing data at an input clock frequency, and applying the stored data at an adjustable output clock frequency, comprising:

first and second memory means for receiving said data at said input clock, storing said data, and applying said data therefrom at said output clock;

switch means for transmitting said data at said input clock for storage in one of said first and second memory means, while transmitting stored data from the other one of said first and second memory means at said output clock;

means coupled to said first and second memory means, respectively, to indicate when a predetermined amount of said stored data has been applied therefrom, and to provide responsively a memory switching signal;

said switch means being further coupled to receive said memory switching signal and to responsively switch between said first and second memory means;

stable oscillator means providing an oscillating signal having a selected fixed frequency;

frequency divider means having an adjustable dividing ration, for receiving said oscillating signal, and for providing a frequency divided output signal, corresponding to said output clock;

means for detecting said output clock frequency with respect to a reference signal, and for providing a first control signal when said detected frequency is higher than a predetermined multiple of said reference signal frequency, and a second control signal when said detected frequency is lower; and

dividing ratio adjustment means for receiving said first and second control signal and for adjusting responsively said dividing ratio of said frequency dividing means to change the frequency of said output clock to substantially correspond to said predetermined multiple of said reference signal frequency.

2. The system of claim 1 wherein said means for detecting said output clock frequency comprises and event detector means coupled to detect occurrence of a signal derived from said frequency divided output signal with respect to said reference signal, and to provide said first control signal in response to an early occurrence, and said second control signal in response to a late occurrence of said derived signal.

3. The system of claim 2 wherein said means for detecting said output clock frequency further comprises counter means coupled to receive said output clock, to count a predetermined number of consecutive cycles thereof, to obtain said signal derived from said frequency divided output signal.

4. The system of claim 2 wherein said occurrence of said signal derived from said frequency divided output signal corresponds to an occurrence of said memory switching signal.

5. A system for receiving data recovered from a magnetic recording medium by a magnetic transducer mounted on a rotating scanner drum, said system receiving said data at a first clock rate, storing said data in a memory, and outputting said stored data from said memory at a second clock rate which is substantially lower than said first clock rate, comprising:

first and second memory means coupled to receive and store said recovered data at said first clock rate;

switch means coupled to transmit said recovered data at said first clock rate to one of said first and second memory means, respectively, and to transmit a second clock signal of said second rate to the other one of said memory means, for outputting stored data therefrom, said switch means being further coupled to switch said respective signals transmitted thereby between said first and second memory means in response to a memory switching signal indicating a predetermined level of fullness of one said memory means;

means for detecting occurrence of said memory switching signal with respect to a reference signal derived from a rotation of said scanner;

oscillator means providing an oscillating output signal having a selected fixed frequency;

frequency divider means having an adjustable dividing ratio, coupled to receive said output signal provided by said oscillator means and to provide a frequency divided output signal having a nominal frequency corresponding to said second clock rate;

means responsive to said detecting means and coupled to said frequency divider means for increasing said dividing ratio thereof in response to an early occurrence of said memory switching signal, and for decreasing said dividing ratio in response to a late occurrence of said memory switching signal with respect to said reference signal; and

wherein

said frequency divided output signal is applied to said switch means as said second clock signal.