Method for the manufacture of multilayer printed circuit boards

• US 4,897,338 A
• Filed: 08/03/1987
• Issued: 01/30/1990
• Est. Priority Date: 08/03/1987
• Status: Expired due to Fees

• Current Assignee: Alliedsignal Inc.
• Original Assignee: Alliedsignal Inc.
• Inventors: Spicciati, Frank A., Ilardi, Joseph M., Fraenkel, Howard A., Kurtz, Bruce E.
• Primary Examiner(s): Dees, Jose G.
• Application Number:
  US07/080,932
• Time in Patent Office: 911 Days
• Field of Search: 430/313, 430/314, 430/315, 430/317, 430/319, 430/316, 430/318, 430/312, 430/394, 204/15
• US Class Current: 430/314
• CPC Class Codes: G01N 2035/041 lifting items out of a rack for access
• CPC Class Codes: H05K 1/0206 by printed thermal vias
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/053 the metal substrate being covered by an inorganic insulating layer
• CPC Class Codes: H05K 1/056 the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 2201/09563 Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2203/0733 Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/181 by electroless plating adhesives therefor H05K3/387
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

This method relates to a process for manufacturing printed circuit boards having high density, fine lines of printed conductors. Extremely straight, vertical walls are formed in the radiation light curable dielectric material.

Claims

1. A process for manufacturing a printed circuit board which comprises the steps of:

(a) applying a first layer of a radiation curable dielectric material to a given area of a substrate;

(b) placing a photomask defining a first conductor circuit pattern adjacent to the surface of said first layer of said curable dielectric material;

(c) exposing said material to a source of radiation and developing said material to expose those regions of said substrate where a first conductor circuit pattern is to be formed;

(d) forming a first conductor circuit pattern on the surface of said substrate by plating a metal coating over those regions of said substrate covered by said exposed first layer of said curable material to provide a printed circuit board of which the first layer of said dielectric material is a structural element, said forming step (d) comprising steps (e) to (i);

(e) electrolessly plating a metal coating onto the exposed surfaces of said substrate where said first conductor circuit pattern is to be formed thereby forming a portion of said first circuit pattern, and plating said coating onto the surface of said first layer of said dielectric material;

(f) applying a first layer of a plating resist to said coating;

(g) placing a photomask defining said first conductor circuit pattern adjacent to the surface of said first layer of said resist;

(h) exposing said resist to a source of radiation and developing said resist to expose those regions of said substrate where a first conductor circuit pattern is to be formed;

(i) plating a second metal coating onto those regions of said electrolessly plated metal coating where said circuit pattern is to be formed forming the remainder of said first conductor circuit pattern;

(j) forming a second conductor circuit pattern on the surface of said first layer of said radiation curable material, said second conductor circuit pattern forming step (j) comprising steps (k) to (o);

(k) removing the remainder of said first plating resist and applying a second layer of plating resist to the surface of said electrolessly plated coating and to said first conductor circuit pattern;

(l) placing a photomask defining a second conductor circuit pattern adjacent to the surface of said second layer of said resist;

(m) exposing said second layer of said plating resist to a source of radiation and developing said resist to expose those regions of said electrolessly plated coating and/or said first conductor circuit pattern where said second conductor circuit pattern is to be formed;

(n) forming said second conductor circuit pattern by plating a metal coating onto the exposed regions of electrolessly plated metal coating and/or said first conductor circuit pattern; and

(o) removing plating resist from the surface of the electroless plated metal layer which does not form a part of said second conductor circuit pattern, and removing said metal layer to expose the surfaces of said first layer of radiation curable dielectric material.

2. A process according to claim 1 wherein in step (i) said metal coating is plated onto said exposed regions by electroplating.

3. A process according to claim 1 wherein said second conductor circuit pattern is formed by electroplating said metal coating onto said exposed regions.

4. A process according to claim 1 which further comprises step (p) applying a second layer of radiation curable dielectric material to a given area of said exposed surface of said first layer of radiation curable dielectric material and to a given area of said second conductor circuit pattern and/or said second conductor circuit pattern.

5. A process according to claim 4 wherein the exposed surfaces of said first layer of said material is etched prior to application of said second layer of said material.

6. A process according to claim 1 which further comprises repeating steps (a) to (o) to form at least two additional conductor circuit patterns.

7. A method according to claim 1 wherein said material is selected from the group consisting of polyimides, polyimides/polyamides, polysiloxanes, polyamide/polysiloxanes and epoxy resins.

8. A method according to claim 1 wherein said dielectric constant of said material is less than about 5,000.

9. A method according to claim 8 wherein said dielectric constant is less than about 50.

10. A method according to claim 9 wherein said dielectric constant is less than about 10.

11. A method according to claim 10 wherein said dielectric constant is less than about 5.

12. A method according to claim 1 wherein said substrate is a metal plate.

13. A method according to claim 12 wherein said substrate comprises a multi layer metal plate.

14. A method according to claim 13 wherein the outer metal layer is composed of nickel or copper.

15. A method according to claim 14 wherein said outer metal layer is composed of nickel.

16. A method according to claim 15 wherein said layer is composed of copper.

17. A process for manufacturing a multilayer printed circuit board which comprises the steps of:

(a) applying a first layer of an ultraviolet curable dielectric material to a given area of a substrate having an electrically conductive surface;

(b) placing a photomask defining a first conductor circuit pattern adjacent to the surface of said first layer of said curable dielectric material;

(c) exposing said material to a source of ultraviolet radiation and developing the exposed material to remove said exposed materials from regions of said substrate forming voids in said material where a first conductor circuit pattern is to be formed;

(d) electrolessly plating a metal coating onto those regions of said substrate defining said voids thereby forming a portion of said first conductor circuit pattern, and plating said metal coating onto the surfaces of said unexposed first layer of said ultraviolet curable material;

(e) applying a first layer of a plating resist to the surface of said first layer of said ultraviolet curable dielectric material;

(f) placing a photomask defining said first conductor circuit pattern adjacent the surface of said first layer of said plating resist, the pattern defined by said photomask being congruent with the voids in said first layer of said ultraviolet curable material;

(g) exposing and developing said resist to remove said exposed resist from regions of said surface of said electroless plated metal coating defining said voids;

(h) forming the remainder of said first conductor circuit pattern by electro plating a second metal coating upon the surface of said electroless plated metal layer defining said voids;

(i) removing the remainder of said first layer of said plating resist from the surface of said electroless plated metal coating to expose the surface of said electroless plated metal coating covering the unexposed surface of said first layer of said curable material;

(j) applying a second layer of a plating resist to the surfaces of said exposed electroless plated metal coating;

(k) placing a photomask defining a second conductor circuit pattern adjacent to the surface of said second layer of said plating resist, and exposing and developing said resist to remove said exposed resist from regions of said electroless plated metal coating where said second conductor circuit is to be formed;

(1) forming said second conductor circuit pattern by electroplating a second metal coating onto said exposed electroless plated metal coating where said second conductor circuit pattern is to be formed;

(m) removing the remainder of said second layer of said plating resist from the surface of said electroless plated metal coating to expose said metal layer, and removing said exposed metal coating from the surface of said first dielectric radiation curable layer to exposing said layer; and

(n) applying a second layer of dielectric radiation curable material over a given area of the said first conductor circuit pattern, said second conductor circuit pattern and/or said exposed first radiation curable layer and repeating steps (b) to (1) to form at least one additional conductor circuit layer.