Semiconductor wafer array

• US 4,897,708 A
• Filed: 07/17/1986
• Issued: 01/30/1990
• Est. Priority Date: 07/17/1986
• Status: Expired due to Fees

• Current Assignee: Vertical Circuits Solutions, Inc.
• Original Assignee: LaserDynamics Inc.
• Inventors: Clements, Ken
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): Sotomayor, John B.
• Application Number:
  US06/887,129
• Time in Patent Office: 1,293 Days
• Field of Search: 357/65, 357/71, 357/75, 357/82, 357/68
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4823 connecting the wire to a pin of the item
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

A wafer array comprising a plurality of wafers of semiconductor material are stacked one on top of another. Through holes are provided in the wafers and electrically conductive liquid is inserted in the through holes for interconnecting all of the wafers. The conductive liquid is electrically insulated from all parts of the wafers except a part comprising an electrically conductive bonding pad which provides an electrical path between the conductive liquid and transistors located in the wafers. The wafers, which are disposed in a stack one on top of the other, are mounted in an enclosure and coupled to electrical pin members for connection to external devices.

Claims

1. A wafer array comprising:

a plurality of wafers of material which are disposed in a stack one on top of another;

a through-hole in each of said wafers in said stack, said through-hole having an apex at one surface of said wafer and a base at the opposite surface of said wafer with an outwardly sloping sidewall extending from said apex to said base.

first retaining means for retaining said through-hole in one of said wafers in said stack in registration with said through-hole in an adjacent wafer in said stack;

an electrically conductive pad located adjacent to said apex of said through-hole in each of said wafers, said base of said through-hole being large enough to extend over the electrically conductive pad located adjacent to said apex of a through-hole in registration therewith on an adjacent wafer;

an electrically conductive liquid which extends through said through-hole in each of said wafers for electrically connecting said electrically conductive pad on one of said wafers with said electrically conductive pad on said adjacent wafer;

means for electrically isolating said electrically conductive liquid from exposed surfaces of said wafer material; and

second and third retaining means located on the top and bottom of said stack, respectively for retaining said electrically conductive liquid in said through-holes, said third retaining means including means for electrically connecting said electrically conductive liquid to an external device.

2. An array according to claim 1 wherein each of said plurality of wafers comprises a transistor means and means for coupling said transistor means to said electrically conductive pad means.

3. An array according to claim 2 wherein said wafers comprise wafers of semiconductor material and said transistor means comprises integrated transistor circuit means.

4. An array according to claim 3 wherein said transistor means comprises a memory cell.

5. An array according to claim 1 wherein said through-hole comprises:

a cone-shaped through-hole.

6. An array according to claim 1 wherein said plurality of wafers comprises more than two of said wafers, said first retaining means comprises means for retaining said through-hole in each of said wafers in registration with said through-hole in said other wafers and said electrically conductive liquid extends through all of said through-holes in registration for electrically connecting said electrically conductive pads adjacent said through-holes on all of said wafers.

7. An array according to claim 1 wherein said first retaining means comprises an adhesive for adhesively attaching adjacent ones of said wafers to each other.

8. An array according to claim 1 wherein said electrically conductive liquid comprises mercury.

9. An array according to claim 1 wherein said isolating means comprises polyimide.

10. An array according to claim 1 wherein said isolating means comprises an oxide.

11. A wafer array comprising:

a stack of wafers of semiconductor material, each of said wafers having transistor means located therein and a through-hole extending through said wafer, said through-hole having an apex at one surface of said wafer and a base at the opposite surface of said wafer with an outwardly sloping sidewall extending from said apex to said base;

an electrically conductive pad located adjacent to said apex of said through-hole in each of said wafers, said base of said through-hole being large enough to extend over the electrically conductive pad located adjacent to said apex of a through-hole in registration therewith on an adjacent wafer, said electrically conductive pad on each of said wafers being electrically connected to said transistor means located therein; and

means, including an electrically conductive liquid which extends through the through-hole in each of said wafers in said stack, for electrically interconnecting said electrically conductive pads adjacent to said through-holes in registration on all of said wafers.

12. A wafer array according to claim 11 comprising means for electrically isolating all surfaces of each of said wafers other than said electrically conductive pad from said electrically conductive liquid.

13. A wafer array according to claim 12 wherein said isolating means comprises a layer of electrically non-conductive material which covers the walls of each of said through-holes and said array further comprises a layer of electrically conductive material which overlays said layer of electrically non-conductive material in said through-hole and is in electrical contact with said electrically conductive pad adjacent to said through-hole for providing a lower resistance to current flow through said through-hole than is obtainable with said electrically conductive liquid alone.

14. A wafer array according to claim 11 comprising an interconnection wafer which is wider than said wafers in said stack and has an electrically conductive trace, one end of which is located in registration with a column of said through-holes and a second end of which is adapted to be electrically connected to a connecting member for electrically connecting said electrically conductive liquid to an external device.

15. A wafer array according to claim 14 wherein said interconnection wafer is located on one end of said stack and comprising means located on the opposite end of said stack for sealing said conductive liquid in said through-holes.

16. A method of making a wafer array comprising the steps of:

providing a plurality of wafers, each of said wafers having an electrically conductive pad located on at least one surface thereof;

coating said pad and the surface of said wafer surrounding said pad with a protective layer of material;

providing a through-hole which extends through said protective layer of material, said pad and the wafer beneath said pad, said protective layer providing protection for the underlying wafer surface during said step of providing said through-hole;

coating both sides of said wafer, said first protective layer and the walls of said through-hole with an electrically non-conductive layer;

removing said protective layer and said electrically non-conductive layer covering said pad and said surface of said wafer surrounding said pad;

coating at least one surface of each of said wafers with a non-electrically conductive adhesive for bonding one wafer to another after they have been placed in a stacked relationship;

stacking said plurality of wafers one on top of another in such a manner that said through-hole in each of said wafers is in registration with said through-hole in the wafers adjacent thereto and said pad and the surfaces of said through-hole are kept free of said adhesive;

attaching one end of the stacked wafers to an interconnection wafer, said interconnection wafer having an electrically conductive trace which extends from an exterior pad in registration with said through-holes to an exterior pad near the periphery thereof;

placing a supply of electrically conductive liquid on the opposite end of said stack over said through-holes;

placing said stack with said interconnection wafer and said supply of electrically conductive liquid in a vacuum chamber;

evacuating said chamber so as to evacuate said through-holes;

allowing said chamber to recover to atmospheric pressure after said through-holes have been evacuated so as to cause said electrically conductive liquid to migrate into said evacuated through-holes;

covering said stack with a material for retaining said electrically conductive liquid in said through-holes;

mounting said stack in a case on a layer of compliant material; and

attaching said external pad on said periphery of said interconnection wafer to an electrical pin member which extends through a wall of said case for providing a means for electrically connecting said stack to an external device.