Semiconductor device

• US 4,897,710 A
• Filed: 08/18/1987
• Issued: 01/30/1990
• Est. Priority Date: 08/18/1986
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Suzuki, Akira, Hatano, Akitsugu, Furukawa, Katsuki, Uemoto, Atsuko
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Loke, Steven H.
• Application Number:
  US07/086,490
• Time in Patent Office: 896 Days
• Field of Search: 357/71, 357/65, 357/30, 357/68, 357/2, 357/16, 357/23.15, 357/23.14, 357/61, 357/23.1
• US Class Current: 257/77
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The semiconductor device comprises a silicon substrate, a boron-doped high resistant silicon carbide layer that is formed on the silicon substrate and a silicon carbide layer formed on the high resistant silicon carbide layer. The silicon carbide layer that is formed on the high resistant silicon carbide layer provides an electrical insulation for the device so that improved device characteristics are obtained.

Claims

1. A structure for a p-n junction gate type FET semiconductor device, comprising:

a substrate;

a first silicon carbide layer disposed on said substrate for electrically insulating said substrate;

a second silicon carbide layer disposed on said first silicon carbide layer for forming an active layer of the semiconductor device, wherein said second silicon carbide layer is electrically insulated from said substrate by said first silicon carbide layer;

a third silicon carbide layer disposed on a first portion of said second silicon carbide layer for forming a channel layer;

a first electrode layer disposed on a second portion of said second silicon carbide layer for forming a source electrode and a drain electrode; and

a second electrode layer disposed on said third silicon carbide layer for forming a gate electrode.

2. A structure as set forth in claim 1, wherein said second silicon carbide layer is formed of a non-doped n-type single crystal silicon layer.

3. A structure as set forth in claim 1, wherein said third silicon carbide layer is formed of a p-type single crystal silicon layer.

4. A structure as set forth in claim 1, wherein said first electrode layer is formed of Ni.

5. A structure as set forth in claim 1, wherein said second electrode is formed of an aluminum-silicon alloy.

6. A structure for a semiconductor resistor, comprising:

a substrate;

a first silicon carbide layer disposed on said substrate for electrically insulating said substrate;

a second silicon carbide layer disposed on said first silicon carbide layer for forming a resistive layer of the semiconductor resistor, wherein said second silicon carbide layer is electrically insulated from said substrate by said first silicon carbide layer and said second silicon carbide layer is formed of a nitrogen doped-type single crystal silicon layer; and

an electrode layer disposed on said second silicon carbide layer for forming a pair of ohmic electrodes for the resistor.

7. A structure as set forth in claim 6, wherein an amount of nitrogen doped in said second silicon carbide layer determines a resistivity value of the resistor.

8. A structure for a semiconductor capacitor, comprising:

a substrate;

a first silicon carbide layer disposed on said substrate for electrically insulating said substrate;

a second silicon carbide layer disposed on said first silicon carbide layer for forming a bottom plate layer of the semiconductor capacitor, wherein said second silicon carbide layer is electrically insulated from said substrate by said first silicon carbide layer;

a dielectric layer disposed on a first portion of said second silicon carbide layer for forming a capacitance layer;

a first electrode layer disposed on a second portion of said second silicon carbide layer for forming a first electrode contacted to said second silicon carbide layer, thereby forming a bottom plate; and

a second electrode layer disposed on said dielectric layer for forming a top plate of the capacitor.

9. A structure as set forth in claim 8, wherein said second silicon carbide layer is formed of an n-type single crystal silicon layer.

10. A structure as set forth in claim 9, wherein said n-type single crystal silicon layer has a second predetermined resistivity less than 0.1 ohm cm.

11. A structure as set forth in claim 10, wherein said n-type single crystal silicon layer is nitrogen doped.

12. A structure as set forth in claim 8, wherein said dielectric layer is formed of an oxide layer.

13. A structure as set forth in claim 8, wherein said first electrode is formed of Ni.

14. A structure as set forth in claim 8, wherein said second electrode is formed of Al.