Semiconductor integrated circuit and manufacturing method therefor

• US 4,898,839 A
• Filed: 11/15/1988
• Issued: 02/06/1990
• Est. Priority Date: 11/15/1988
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Sadakata, Toshimasa, Sano, Yoshiaki, Sekikawa, Nobuyuki, Fujinuma, Chikao, Takada, Tadayoshi, Tabata, Teruo
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Nguyen, Tuan
• Application Number:
  US07/271,746
• Time in Patent Office: 448 Days
• Field of Search: 437/33, 437/47, 437/919, 437/60, 437/31, 437/46, 148/DIG. 14, 357/51, 357/34
• US Class Current: 438/329
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/8248 Combination of bipolar and field-effect technology
• CPC Class Codes: H01L 27/0658 Vertical bipolar transistor in combination with resistors or capacitors
• CPC Class Codes: Y10S 148/014 Capacitor

Abstract

A method of manufacturing a semiconductor integrated circuit comprises the steps of: forming an epitaxial layer covering a semiconductor substrate and buried layers; forming isolation regions dividing the epitaxial layer into a plurality of islands; forming a lower electrode region of an MIS type capacitor in one of the islands; forming a base region of a vertical bipolar transistor simultaneously with or independently from the lower electrode in another island; depositing a thin dielectric layer of the MIS type capacitor on a portion of the lower electrode region; thereafter selectively diffusing impurities into the surface layer of the base region so as to form an emitter region of the vertical bipolar transistor; and forming an upper electrode of the MIS type capacitor on the thin dielectric layer.

Claims

1. A method for manufacturing a semiconductor integrated circuit comprising the steps of:

preparing a semiconductor substrate of a first conductivity type;

forming buried layers of a second conductivity type on prescribed regions of the substrate;

forming an epitaxial layer of the second conductivity type covering said substrate and said buried layers;

forming isolation regions of the first conductivity type dividing said epitaxial layer into a plurality of islands and simultaneously forming a lower electrode region of a MIS type capacitor in one of said islands;

forming a base region of a vertical bipolar transistor by selectively introducing impurities of the first conductivity type into another island;

covering said epitaxial layer with an oxide layer;

exposing a portion of said lower electrode region by patterning said oxide layer and depositing thereon a dielectric layer of the MIS type capacitor;

further patterning said oxide layer and forming an emitter region of the vertical bipolar transistor by selectively diffusing impurities of the second conductivity type; and

forming an upper electrode of the MIS type capacitor on said dielectric layer and forming electrodes which make ohmic contacts through contact holes provided at desired regions in said oxide layer.

2. A method according to claim 1, wherein a second lower electrode region overlapping with a surface layer of said first lower electrode region is formed simultaneously with the formation of said base region.

3. A semiconductor integrated circuit comprising:

a semiconductor substrate of a first conductivity type;

buried layers of a second conductivity type formed on prescribed regions of said substrate;

an epitaxial layer of the second conductivity type formed covering said substrate and said buried layers;

isolation regions of the first conductivity type formed to divide said epitaxial layer into a plurality of islands;

a lower electrode region of an MIS type capacitor formed in one of said islands simultaneously with said isolation regions such that it extends from an upper surface of said one of the islands to corresponding one of said buried layers;

a base region of a vertical bipolar transistor formed by selectively introducing impurities of the first conductivity type into another island;

a thin dielectric layer of the MIS type capacitor formed on a portion of said lower electrode region;

an emitter region of the vertical bipolar transistor formed by selectively diffusing impurities of the second conductivity type; and

an upper electrode formed on the thin dielectric layer of the MIS type capacitor.

4. A semiconductor integrated circuit according to claim 3, further comprising a second lower electrode region formed simultaneously with said base region and overlapping with a surface layer of said first lower electrode region.

5. A method for manufacturing a semiconductor integrated circuit comprising the steps of:

preparing a semiconductor substrate of a first conductivity type;

forming buried layers of a second conductivity type on prescribed regions of the substrate;

forming an epitaxial layer of the second conductivity type to cover said substrate and said buried layers;

forming isolation regions of the first conductivity type dividing said epitaxial layer into a plurality of islands and simultaneously forming a lower electrode region of an MIS type capacitor on one of said islands;

exposing said epitaxial layer by removing a thick thermal oxide layer inevitably formed on said epitaxial layer when forming said isolation regions, and again forming a thin thermal oxide layer on said surface of said epitaxial layer;

implanting impurity ions of the first conductivity type into another island through said thin oxide layer in order to form a base region of a vertical bipolar transistor;

forming a thin dielectric layer of the MIS type capacitor on said lower electrode region; and

forming an emitter region of the vertical bipolar transistor to a prescribed thickness by selectively diffusing impurities of the second conductivity type into said epitaxial layer.

6. A method according to claim 5, wherein lower regions of said isolation regions are formed by diffusion from impurity seeds provided on said substrate to surround said buried layers, and upper regions of said isolation regions are formed by diffusion from impurity seeds applied on an upper surface of said epitaxial layer.

7. A method according to claim 5, wherein a second lower electrode region overlapping with a surface layer of said first lower electrode region is formed simultaneously with the formation of said base region.

8. A method for manufacturing a semiconductor integrated circuit comprising the steps of:

preparing a semiconductor substrate of a first conductivity type;

forming buried layers of a second conductivity type on prescribed regions of the substrate;

forming an epitaxial layer of the second conductivity type covering said substrate and said buried layers;

forming isolating regions dividing said epitaxial layer into a plurality of islands by selectively diffusing impurities of the first conductivity type into said epitaxial layer;

forming a collector low resistance region of a vertical bipolar transistor extending from an upper surface of one of said islands to corresponding one of said buried layers by selectively diffusing impurities of the second conductivity type from an upper surface of said epitaxial layer and simultaneously forming a lower electrode region of an MIS type capacitor in another island;

forming a base region of the vertical bipolar transistor by selectively diffusing impurities of the first conductivity type into said one of the islands;

covering said epitaxial layer by an oxide layer;

exposing a portion of said lower electrode region by patterning said oxide layer and depositing thereon a thin dielectric layer of an MIS type capacitor;

forming an emitter region of the vertical bipolar transistor by further patterning said oxide layer and by selectivity diffusing impurities of the second conductivity type into said one of the islands; and

forming an upper electrode of the MIS type capacitor on said thin dielectric layer and forming an electrode on a desired region which makes an ohmic contact through a contact hole provided in said oxide layer.