Flex dot wafer probe
First Claim
1. For use in testing the electrical integrity and performance of at least one integrated circuit formed on a semiconductor wafer, a wafer probe test system including a flex dot wafer probe and external test equipment having signal transmitting elements disposed in a predetermined pattern for providing electrical test signals to test the electrical integrity and performance of each integrated circuit, and wherein each integrated circuit to be tested includes a predetermined pattern of contact elements adapted to receive the electrical test signals, said flex dot wafer probe comprising;
- probe board means having test equipment contact elements for electrically interfacing with corresponding signal transmitting elements of the external test equipment, said probe board means further including interface contact pads arranged in a predetermined pattern; and
wafer probe head means disposed in combination with said probe board means for interfacing between said probe board means and each integrated circuit to be tested, said wafer probe head means includingfilm means configured for resiliently interfacing between the interface contact pads of said probe board means and the contact elements of each integrated circuit to be tested to provide electrical continuity therebetween for the electrical test signals, said film means configured to include a base plane and at least one tab extending from said base plane in a U-shaped profile such that said at least one tab is approximately parallel to said base plane, andsupport member means having first and second major surfaces for mounting said film means wherein said base plane of said film means is mounted on said first major surface and each said at least one tab is mounted on said second major surface,said film means further includinga plurality of protrusions formed one each said at least one tab of said film means in a mirror-image pattern corresponding to said predetermined pattern of said interface contact pads, said protrusions being forcibly urged into physical and electrical engagement with said interface contact pads in a nondeformable manner to provide electrical continuity therebetween for the electrical test signals,a plurality of wafer contact pads formed on said base planes of said film means in a mirror-image pattern corresponding to the predetermined pattern of the contact elements of each integrated circuit to be tested, said wafer contact pads being forcibly urged into physical and electrical engagement with corresponding contact elements of each integrated circuit to be tested in a scrubbing and nondeformable manner to provide enhanced electrical continuity therebetween for the electrical test signals, andcoplanar line conductor means formed on said film means for electrically interconnecting said protrusions to corresponding ones of said wafer contact pads to provide electrical continuity between said probe board means and the integrated circuit chip to be tested wherein electrical test signals from the test equipment are transmitted to said probe board means and to said wafer probe head means via said forcibly engaged interface contact pads and said protrusions, and wherein the electrical test signals are further transmitted from said protrusions via said coplanar line conductor means to said plurality of wafer contact pads and through said forcibly engaged wafer contact pads and the contact elements of the integrated circuit to be tested to the integrated circuit to determine the electrical integrity and performance of the integrated circuit.
1 Assignment
0 Petitions
Accused Products
Abstract
A flex dot wafer probe having utility as an electrical interface between semiconductor wafers and electronic test systems for determining the electrical integrity and performance of integrated circuits. The wafer probe comprises a wafer probe head having a preformed resilient, bendable, formable film mounted on a support member for flexible movement. The wafer probe head is integrated with a probe board which interfaces with an external test system. Wafer contact pads and protrusions are formed on the film in "mirror-image" patterns corresponding to the contact elements of the integrated circuits and interface contact pads of the probe board, respectively. Coplanar line conductors, formed to control the characteristic impedance of the wafer probe head, provide electrical continuity between the wafer contact pads and the protrusions. The conductive protrusions formed on the wafer contact pads and the film physically and electrically engage the contact elements of the integrated circuits and the probe board, respectively, thereby providing electrical paths for test signals between the external test system and the integrated circuits. The flexible configuration of the wafer probe head ensures that all protrusions are forcibly urged into physical and electrical engagement with the corresponding external contact elements at an acceptable force level which precludes deformation of the protrusions.
-
Citations
19 Claims
-
1. For use in testing the electrical integrity and performance of at least one integrated circuit formed on a semiconductor wafer, a wafer probe test system including a flex dot wafer probe and external test equipment having signal transmitting elements disposed in a predetermined pattern for providing electrical test signals to test the electrical integrity and performance of each integrated circuit, and wherein each integrated circuit to be tested includes a predetermined pattern of contact elements adapted to receive the electrical test signals, said flex dot wafer probe comprising;
-
probe board means having test equipment contact elements for electrically interfacing with corresponding signal transmitting elements of the external test equipment, said probe board means further including interface contact pads arranged in a predetermined pattern; and wafer probe head means disposed in combination with said probe board means for interfacing between said probe board means and each integrated circuit to be tested, said wafer probe head means including film means configured for resiliently interfacing between the interface contact pads of said probe board means and the contact elements of each integrated circuit to be tested to provide electrical continuity therebetween for the electrical test signals, said film means configured to include a base plane and at least one tab extending from said base plane in a U-shaped profile such that said at least one tab is approximately parallel to said base plane, and support member means having first and second major surfaces for mounting said film means wherein said base plane of said film means is mounted on said first major surface and each said at least one tab is mounted on said second major surface, said film means further including a plurality of protrusions formed one each said at least one tab of said film means in a mirror-image pattern corresponding to said predetermined pattern of said interface contact pads, said protrusions being forcibly urged into physical and electrical engagement with said interface contact pads in a nondeformable manner to provide electrical continuity therebetween for the electrical test signals, a plurality of wafer contact pads formed on said base planes of said film means in a mirror-image pattern corresponding to the predetermined pattern of the contact elements of each integrated circuit to be tested, said wafer contact pads being forcibly urged into physical and electrical engagement with corresponding contact elements of each integrated circuit to be tested in a scrubbing and nondeformable manner to provide enhanced electrical continuity therebetween for the electrical test signals, and coplanar line conductor means formed on said film means for electrically interconnecting said protrusions to corresponding ones of said wafer contact pads to provide electrical continuity between said probe board means and the integrated circuit chip to be tested wherein electrical test signals from the test equipment are transmitted to said probe board means and to said wafer probe head means via said forcibly engaged interface contact pads and said protrusions, and wherein the electrical test signals are further transmitted from said protrusions via said coplanar line conductor means to said plurality of wafer contact pads and through said forcibly engaged wafer contact pads and the contact elements of the integrated circuit to be tested to the integrated circuit to determine the electrical integrity and performance of the integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. For use in testing the electrical integrity of at least one integrated circuit formed on a semiconductor wafer, a probe test system including a flex dot wafer probe and external test equipment having signal transmitting elements disposed in a predetermined pattern for providing electrical test signals to test the electrical integrity and performance of each integrated circuit, and wherein each integrated circuit includes a predetermined pattern of contact elements adapted to receive the electrical test signals, said flex dot wafer probe comprising:
-
a probe board for interfacing with the external test equipment, said probe board including interface contact pads having a predetermined pattern, means for electrically interfacing with the signal transmitting elements of the external test equipment, and means for electrically interconnecting said interface contact pads and said electrical interface means; a wafer probe head configured to be forcibly urged into physical and electrical engagement with said probe board and to interface with each integrated circuit to be tested, said wafer probe head including a resilient bendable film having a base plane and at least one tab extending from said base plane with the extremity thereof disposed approximately planar to said base plane, a plurality of protrusions formed on each said at least one tab in a mirror-image pattern corresponding to said predetermined pattern of said interface contact pads of said probe board, said plurality of protrusions being forcibly urged into physical and electrical engagement with said interface contact pads in a nondeformable manner to provide electrical continuity therebetween for the electrical test signals, a plurality of wafer contact pads formed on said base plane in a mirror-image pattern corresponding to said predetermined pattern of the contact elements of each integrated circuit to be tested, said wafer contact pads being forcibly urged into physical and electrical engagement with corresponding contact elements of each integrated circuit to be tested in a scrubbing and nondeformable manner to provide enhanced electrically continuity therebetween for the electrical test signals, and a plurality of coplanar line conductors formed on said base plane and said tabs to electrically interconnect corresponding ones of said plurality of protrusions and said plurality of wafer contact pads wherein the electrical test signals are transmitted from said interface contact pads to said plurality of protrusions, from said plurality of protrusions to said wafer contact pads via said plurality of coplanar line conductors and from said wafer contact pads to the contact elements of the integrated circuit to be tested to determine the electrical integrity and performance of the integrated circuit. - View Dependent Claims (14, 15, 18)
-
-
13. For use in testing the electrical integrity of at least one integrated circuit formed on a semiconductor wafer, a probe test system including a flex dot wafer probe and external test equipment having signal transmitting elements disposed in a predetermined pattern for providing electrical test signals to test the electrical integrity and performance of each integrated circuit, and wherein each integrated circuit includes a predetermined pattern of contact elements adapted to receive the electrical test signals, said flex dot wafer probe comprising:
-
a probe board for interfacing with the external test equipment, said probe board including interface contact pads having a predetermined pattern, means for electrically interfacing with the signal transmitting elements of the external test equipment, and means for electrically interconnecting said interface contact pads and said electrical interface means; a wafer probe head configured to be physically and electrically integrated with said probe board and to interface with each integrated circuit to be tested, said wafer probe head including a resilient bendable film having a base plane and tabs extending from said base plane with extremities thereof disposed approximately planar said base plane, a plurality of protrusions formed on said tabs in a mirror-image pattern corresponding to said predetermined pattern of said interface contact pads of said probe board, said plurality of protrusions physically and electrically engaging said interface contact pads in a nondeformable manner to provide electrical continuity therebetween for the electrical test signals, a plurality of wafer contact pads formed on said base plane in a mirror-image pattern corresponding to said predetermined pattern of the contact elements of each integrated circuit to be tested, said wafer contact pads physically and electrically engaging corresponding contact elements of each integrated circuit to be tested in a scrubbing and nondeformable manner to provide enhanced electrical continuity therebetween for the electrical test signals, a plurality of coplanar line conductors formed on said base plane and said tabs to electrically interconnect corresponding ones of said plurality of protrusions and said plurality of wafer contact pads wherein the electrical test signals are transmitted from said interface contact pads to said plurality of protrusions, from said plurality of protrusions to said wafer contact pads via said plurality of coplanar line conductors and from said wafer contact pads to the contact elements of the integrated circuit to be tested to determine the electrical integrity and performance of the integrated circuit, and a support member having first and second major surfaces, said film being mounted on said support member to have said base plane adjacent said first major surface and said tabs adjacent said second major surface, said support member further including resilient pressure pads disposed on said first and second major surfaces in registration with said plurality of wafer contact pads and said plurality of protrusions, respectively, to control flexile movement of said film wherein said plurality of wafer contact pads engage corresponding contact elements of each integrated circuit to be tested in said scrubbing and nondeformable manner to provide enhanced electrical continuity therebetween for the electrical test signals and said plurality of protrusions engage corresponding interface contact pads of said probe board said nondeformable manner to provide electrical continuity therebetween for the electrical test signals and said plurality of protrusions. - View Dependent Claims (16, 17)
-
-
19. A method for testing the electrical integrity and performance of at least one integrated circuit formed on a semiconductor wafer using external test equipment having signal transmitting elements disposed in a predetermined pattern to provide electrical test signals to test the electrical integrity and performance of each integrated circuit, and wherein each integrated circuit to be tested includes a predetermined pattern of contact elements adapted to receive the electrical test signals, comprising the steps of:
-
forming a flex dot wafer probe for electrically interfacing between the external test equipment and the integrated circuit to be tested, said flex dot wafer probe including a probe board for interfacing with the external test equipment, said probe board having an orientation aperture formed therethrough and further including interface contact pads having a predetermined pattern, means for electrically interfacing with the signal transmitting elements of the external test equipment, and means for electrically interconnecting said interface contact pads and said electrical interface means, a wafer probe head physically and electrically integrated with said probe board and interfacing with each integrated circuit to be tested, said wafer probe head including a support member having first and second major surfaces and a central aperture formed therethrough, a resilient bendable film having a base plane and tabs extending from said base plane with extremities thereof disposed approximately planar said base plane and wafer alignment means formed therethrough for aligning said flex dot wafer probe with the integrated circuit to be tested, said wafer alignment means in combination with said orientation aperture and said central aperture forming an unobstructed line-of-sight through said flex dot wafer probe along the Z-axis thereof, said film being mounted on said support member to have said base plane adjacent said first major surface and said tabs adjacent said second major surface, a plurality of protrusions formed on said tabs in a mirror-image pattern corresponding to said predetermined pattern of said interface contact pads of said probe board, said plurality of protrusions physically and electrically engaging said interface contact pads in a nondeformable manner to provide electrical continuity therebetween for the electrical test signals, a plurality of wafer contact pads formed on said base plane in a mirror-image pattern corresponding to said predetermined pattern of the contact elements of each integrated circuit to be tested, said wafer contact pads physically and electrically engaging corresponding contact elements of each integrated circuit to be tested in a scrubbing and nondeformable manner to provide enhanced electrical continuity therebetween for the electrical test signals, and a plurality of coplanar line conductors formed on said base plane and said tabs to electrically interconnect corresponding ones of said plurality of protrusions and said plurality of wafer contact pads; aligning said flex dot wafer probe with the integrated circuit to be tested by positioning said wafer alignment means along edges of the integrated circuit to be tested, solving equations based upon known dimensions of said wafer alignment means, said wafer contact pads, the edges of the integrated circuit to be tested and the contact elements of the integrated circuit to be tested to generate Δ
X, Δ
Y and Δ
θ
values to align said wafer contact pads and the contact elements in registration for testing, andeffecting relative coplanar shifting between said wafer contact pads and the contact elements of the integrated circuit to be tested for registration thereof; effecting Z-axis movement of said flex dot wafer probe to bring said wafer contact pads and the contact elements of the integrated circuit to be tested in physical and electrical engagement in a nondeformable manner to provide electrical continuity therebetween for the electrical test signals; effecting relative micromovement between said physically engaged wafer contact pads and the contact elements to scrub oxide films therefrom to enhance the electrical continuity therebetween; and providing electrical test signals from the external test equipment to the signal transmitting elements, the electrical test signals being transmitted to said interface contact pads, from said interface contact pads to said plurality of protrusions, from said plurality of protrusions to said wafer contact pads via said plurality of coplanar line conductors and from said wafer contact pads to the contact elements of the integrated circuit to be tested to determine the electrical integrity and performance of each integrated circuit to be tested.
-
Specification