Leading edge detector/reply quantizer

• US 4,899,157 A
• Filed: 04/03/1989
• Issued: 02/06/1990
• Est. Priority Date: 04/03/1989
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Alliedsignal Inc.
• Inventors: Lyons, Bernard J., Yienger, Robert C., Sanford, Norman R.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): Sotomayor, John B.
• Application Number:
  US07/332,135
• Time in Patent Office: 309 Days
• Field of Search: 342/40, 342/45, 342/32, 342/37, 342/46, 342/51, 307/360, 307/247.1
• US Class Current: 342/40
• CPC Class Codes: G01S 13/788 Coders or decoders therefor; Special detection circuits

Abstract

An improved Leading Edge Detector/Pulse Quantizer (LED) for use in a pulse code communications system. A prior LED included three shift registers for storing in relative time order, according to the time of reception of video pulse signals by an associated receiver, (a) pulse leading edges, (b) pulse trailing edges and (c) Quantized video (quantized video comprises a pulse having a width equal to the time the received video exceeds a threshold amplitude). The prior LED further included a plurality of logic means for examining the contents of the three registers to determine whether pulse leading or trailing edges of the received video signal were possibly missing because of interference between received video pulses and for inserting extra leading edges in the leading edge register if such extra leading edges could be logically inferred to be present.

The improvement of the invention includes expansions of the functions of the logic means for detecting and inferring the presence of leading edges and trailing edges, improved control means to insure that the logic means operate in proper sequence and improved logic means for deleting signals from the leading edge register when their presence is determined to be illogical.

Claims

1. In a pulse code communications system having a receiver, a video detector producing a composite video signal which may be formed by interfering pulse signals received by said receiver and a leading edge detector/pulse quantizer for processing said composite video signal to separate interfering pulses therein, said leading edge detector including:

a source of clock signals;

means responsive to the amplitude and rate of change of amplitude of said composite video signal to provide;

(a) a positive slope (PS) signal which persists during the time said rate of change of amplitude increases at a predetermined rate;

(b) a negative slope (NS) signal which persists during the time said rate of change of amplitude decreases at a predetermined rate; and

(c) a quantized video (QV) signal which persists during the time said amplitude exceeds a predetermined level;

a first shift register for propagating said PS signals according to their relative times of appearance;

a second shift register for propagating said NS signals according to their relative times of appearance;

a third shift register for propagating said QV signals according to their relative times of appearance;

each of said first, second and third registers propagating the signals contained therein at a rate determined by said clock signals;

first logic means for examining the contents of said first and third registers to determine the truth of a condition in which;

said third register contains a signal which has persisted for two or more clock signals after the appearance of a first signal in said first register; and

for inserting a signal in said first register at a position two clock signals after said first signal therein if said condition is true;

second logic means for examining the contents of said first and second registers to determine the truth of a condition in which;

a signal is present in said second register at a position of between 11 and 18 clock signals after a first signal appears in said first register and no second signal is present in said first register in said 11-18 clock signal interval; and

for inserting a second signal in said first register at a position corresponding to a time of 7 clock signals before the time of appearance of said signal in said second register; and

means for unloading the contents of said first register in serial-by-bit format after operation of said first and second logic means;

the improvement wherein said first logic means further includes;

means for determining the truth of a second condition in which;

a first and second signal are present in said first register separated by one clock signal interval and said third register contains a signal at the time said first signal of said first register ends; and

means for deleting said second signal from said first register if said second condition is not true.

2. The improvement of claim 1 wherein said source of clock signals generates clock signals at a frequency of substantially 16 MHz and further including:

means included in said first logic means for determining the truth of a third condition in which;

a first signal is present in said first register and no signal is present in said third register at a time corresponding to the time of said first signal in said first register, but a signal does appear in said third register within a time of two clock signals after the end of said first signal in said first register; and

means for deleting said first signal from said first register if said third condition is not true.

3. The improvement of claim 2 further including:

third logic means for examining the contents of said first, second and third registers during first, second and third intervals, respectively,

said first interval extending through a time corresponding to six clock signals prior to a reference clock signal until said reference clock signal,

said second interval extending from a time beginning just before four clock signals prior to said reference clock signal and ending at a time just after one clock signal prior to said reference clock signal,

said third interval extending from a time beginning just before nine clock signals prior to said reference clock signal and ending just after four clock signals after said reference clock signal,

and for determining the truth of a condition in which;

no signal is present in said first register during said first interval and a signal is present in said second register during said second interval and a signal is present in said third register during said entire third interval; and

means for inserting a signal in said first register at a time corresponding to two clock signals after said reference clock signal if said condition of said third logic means is true.

4. The improvement of claim 3 further including:

fourth logic means for examining the contents of said first, second and third registers during fourth, fifth and sixth intervals, respectively,

said fourth interval extending from a time corresponding to nine clock signals prior to a reference clock signal until one clock signal after said reference clock signal,

said fifth interval extending from a time just prior to the second clock signal after said reference clock signal until a time just after said second clock signal,

said sixth interval extending from a time just prior to the fourth clock signal before said reference clock signal until a time just after said reference clock signal;

and for determining the truth of a first condition in which;

no signal is present in said first register during said fourth interval and a signal is present in said second register during said fifth interval and a signal is present in said third register during said sixth interval; and

means for inserting a signal in said first register at a time corresponding to five clock signals prior to said reference clock signal if said condition of said fourth logic means is true.

5. The improvement of claim 4 wherein said fourth logic means further includes:

means for examining the contents of said third register during seventh and eighth intervals,

said seventh interval extending from a time just prior to the fifth clock signal before said reference clock signal until a time just after the first clock signal before said reference clock signal,

said eighth interval extending from a time just prior to the first clock signal after said reference clock signal until a time just after the third clock signal after said reference clock signal,

and wherein said means of said third logic means for determining the truth of a condition further includes means for determining the truth of a second condition in which;

no signal is present in said first register during said fourth interval and a signal is present in said second register during said fifth interval and a signal is present in said third register during said seventh interval and no signal is present in said third register during said eighth interval; and

means for inserting a signal in said first register at a time corresponding to five clock signals prior to said reference clock signal if said second condition of said fourth logic means is true.

6. The improvement of claim 5 wherein:

said seventh interval extends from a time just prior to the sixth clock signal before said reference clock signal until a time just after the second clock signal before said reference clock signal; and

said eighth interval extends from a time just before said reference clock signal until a time just after the second clock signal after said reference clock signal.

7. The improvement of claim 5 wherein:

said seventh interval extends from a time just prior to the seventh clock signal before said reference clock signal until a time just after the third clock signal before said reference clock signal; and

said eighth interval extends from a time just before the first clock signal before said reference clock signal until a time just after the first clock signal after said reference clock signal.

8. The improvement of claim 5 wherein:

said seventh interval extends from a time just prior to the eighth clock signal before said reference clock signal until a time just after the fourth clock signal before said reference clock signal; and

said eighth interval extends from a time just before the second clock signal before said reference clock signal until a time just after said reference clock signal.

9. The improvement of claim 5 wherein:

said seventh interval extends from a time just prior to the ninth clock signal before said reference clock signal until a time just after the fifth clock signal before the said reference clock signal; and

said eighth interval extends from a time just before the third clock signal before said reference clock signal until a time just after the first clock signal before said reference clock signal.

10. The improvement of claim 5 wherein:

said seventh interval extends from a time just prior to the tenth clock signal before said reference clock signal until a time just after the sixth clock signal before the said reference clock signal; and

said eighth interval extends from a time just before the fourth clock signal before said reference clock signal until a time just after the second clock signal before said reference clock signal.

11. The improvement of claim 5 further including:

an insertion counter for determining the times of operation of said second, third and fourth logic means;

fifth logic means providing an output for resetting and preloading said counter; and

a state machine providing an output for enabling said fifth logic means;

said counter accumulating a count of said clock signals after being reset or preloaded and providing output signals indicative of said accumulated count,

said fifth logic means including a decoder receiving said output signals of said counter for generating a maximum count signal when the accumulated count of said counter reaches a predetermined value, and receiving a first input from said first register at a time corresponding to two clock signals after said reference clock signal, and receiving a second input from said second register at a time corresponding to two clock signals after said reference clock signal,

said state machine including a first flip-flop, a second flip-flop and internal logic means,

said state machine internal logic means receiving;

a first input indicating the presence of a signal in said first register at a time corresponding to two clock signals after said reference clock signal,

a second input indicating the presence of a signal in said second register at a time corresponding to two clock signals after said reference clock signal,

a third input indicating the presence of said maximum count signal from said counter,

a fourth input comprised by a feedback signal from the output of said first flip-flop, and

fifth, sixth and seventh inputs comprised by feedback signals from the output of said second flip-flop,

said state machine logic examining the states of said input signals thereto at times corresponding to each clock signal to determine the state into which the output of said first flip-flop will be driven upon the appearance of the clock signal next following said time of examination,

said fifth logic means further including means for determining the truth of a condition in which;

said maximum count signal is present or said first input thereto indicates the presence of a signal at a time of two clock signals after said reference clock signal or said second input thereto indicates the presence of a signal at a time of two clock signals after said reference clock signal, and

means for generating said output from said fifth logic means if said condition thereof is true and said state machine output is an enabling output.

12. The improvement of claim 11 wherein:

said first flip-flop of said state machine generates an output Q₁,

said second flip-flop of said state machine generates an output Q₂,

said state machine being capable of setting each of said outputs Q₁ and Q₂ to a high logic level or a low logic level,

said state machine having four states S0-S3 defined by the logic levels of said outputs Q₁ and Q₂ as follows;

space="preserve" listing-type="tabular">______________________________________ State Q.sub.1 Q.sub.2 ______________________________________ S0 Low Low S1 High Low S2 Low High S3 High High ______________________________________

said maximum count to said state machine, and said first and second inputs thereto, when considered as a three digit binary number with said maximum count input as the most significant digit and said first input thereto as the least significant digit, having an octal number equivalent of value from zero to seven,

said state machine being controlled by said internal logic thereof, when in said S0 state at the time of any said clock signal, to transition to said S1 upon the next following clock signal only if said octal equivalent of said inputs thereto has a value of one or seven and, when in said S1 state at the time of any said clock signal, to transition to said S3 state only if said octal equivalent has a value of one and to transition to said S0 state if said octal equivalent has a value of two, four or six, and, when in said S3 state at the time of any said clock signal, to transition to said S1 state only if said octal equivalent has a value of zero or four,

said Q₁ output, after any of said transitions, comprising said enabling output of said state machine if said Q₁ output is then at a high logic level.

13. The improvement of claim 12 wherein said maximum count of said insertion counter is sixteen clock signals and with additionally:

sixth logic means for examining the contents of said first second and third registers to determine the truth of a condition in which;

a signal is present in said first register at a time corresponding to fourteen clock signals prior to said reference clock signal and no signal is present at a time extending from just before thirteen clock signals prior to said reference clock signal until just after two clock signals after said reference clock signal,

no signal is present in said second register during an interval extending from just before the thirteenth clock signal prior to said reference clock signal until just after the second clock signal after said reference clock signal, and

a signal is present in said third register during an interval extending from just before the thirteenth clock signal before said reference clock signal until just after the fifth clock signal before said reference clock signal; and

means providing a preload signal to said insertion counter to cause said counter to load a count equal to nine when said output signal of said fifth logic means appears if said condition of said sixth means is true.

14. The improvement of claim 12, further including:

seventh logic means for examining the contents of said first, second and third registers to determine the truth of a condition in which;

a signal is present in said third register during the entirety of an interval extending through a time corresponding to just before the third clock signal before said reference clock signal until just after the first clock signal before said reference clock signal, and

no signal is present in said second register during the entirety of an interval extending from just before the second clock signal before said reference clock signal until just after the first clock signal after said reference clock signal and a signal is present in said third register and no signal is present in said third register at a time just before the first clock signal after said reference clock signal, or

a signal is present in said first register at a time just before the second clock signal after said reference clock signal and no signal is present in said third register at the time of said first clock signal after said reference clock signal and a signal is present in said third register at a time just before the second clock signal after said reference clock signal, or

a signal is present in both said first and said second registers at a time just before the first clock signal after said reference clock signal; and

means for inserting a signal in said second register at a time corresponding to the third clock signal after said reference clock signal.

15. The improvement of claim 14, further including:

eighth logic means for examining the contents of said first, second and third registers to determine the truth of a condition in which;

a signal is present in said first register at a time corresponding to the ninth clock signal before said reference clock signal and no signal is present therein from a time from just before the eighth clock signal before said reference clock signal until just after the first clock signal after said reference clock signal, and

no signal is present in said second register during an interval extending from just before the eighth clock signal before said reference clock signal until just after the second clock signal after the second clock signal after said reference clock signal, and

a signal is present in said third register during the entirety of an interval extending from just before the eighth clock signal before said reference clock signal until just after the first clock signal after said reference clock signal; and

means for inserting a signal in said first register at a time corresponding to the second clock signal before said reference clock signal if said condition of said eighth logic means is true.

16. The improvement of claim 14, further including:

eighth logic means for examining the contents of said first, second and third registers to determine the truth of a condition in which;

a signal is present in said first register at a time corresponding to the tenth clock signal before said reference clock signal and no signal is present therein from a time from just before the ninth clock signal before said reference clock signal until just after the first clock signal after said reference clock signal, and

no signal is present in said second register during an interval extending from just before the ninth clock signal before said reference clock signal until just after the second clock signal after the second clock signal after said reference clock signal, and

a signal is present in said third register during the entirety of an interval extending from just before the ninth clock signal before said reference clock signal until just after said reference clock signal; and

means for inserting a signal in said first register at a time corresponding to the third clock signal before said reference clock signal if said condition of said eighth logic means is true.

17. The improvement of claim 14, further including:

eighth logic means for examining the contents of said first, second and third registers to determine the truth of a condition in which;

a signal is present in said first register at a time corresponding to the eleventh clock signal before said reference clock signal and no signal is present therein from a time from just before the tenth clock signal before said reference clock signal until just after the first clock signal after said reference clock signal; and

no signal is present in said second register during an interval extending from just before the tenth clock signal before said reference clock signal until just after the second clock signal after the second clock signal after said reference clock signal, and

a signal is present in said third register during the entirety of an interval extending from just before the tenth clock signal before said reference clock signal until just after the first clock signal before said reference clock signal; and

means for inserting a signal in said first register at a time corresponding to the fourth clock signal before said reference clock signal if said condition of said eighth logic means is true.

18. The improvement of claim 14, further including:

eighth logic means for examining the contents of said first, second and third registers to determine the truth of a condition in which;

a signal is present in said first register at a time corresponding to the twelfth clock signal before said reference clock signal and no signal is present therein from a time rom just before the eleventh clock signal before said reference clock signal until just after the first clock signal after said reference clock signal, and

no signal is present in said second register during an interval extending from just before the eleventh clock signal before said reference clock signal until just after the second clock signal after the second clock signal after said reference clock signal, and

a signal is present in said third register during the entirety of an interval extending from just before the eleventh clock signal before said reference clock signal until just after the second clock signal before said reference clock signal; and

means for inserting a signal in said first register at a time corresponding to the fifth clock signal before said reference clock signal if said condition of said eighth logic means is true.

19. The improvement of claim 14, further including:

eighth logic means for examining the contents of said first, second and third registers to determine the truth of a condition in which;

a signal is present in said first register at a time corresponding to the thirteenth clock signal before said reference clock signal and no signal is present therein from a time from just before the twelfth clock signal before said reference clock signal until just after the first clock signal after said reference clock signal, and

no signal is present in said second register during an interval extending from just before the twelfth clock signal before said reference clock signal until just after the second clock signal after said reference clock signal, and

a signal is present in said third register during the entirety of an interval extending from just before the twelfth clock signal before said reference clock signal until just after the third clock signal before said reference clock signal; and

means for inserting a signal in said first register at a time corresponding to the sixth clock signal before said reference clock signal if said condition of said eighth logic means is true.

20. The improvement of claim 14, further including:

eighth logic means for examining the contents of said first, second and third registers to determine the truth of a condition in which;

a signal is present in said first register at a time corresponding to the fourteenth clock signal before said reference clock signal and no signal is present therein from a time from just before the twelfth clock signal before said reference clock signal until just after the first clock signal after said reference clock signal, and

no signal is present in said second register during an interval extending from just before the thirteenth clock signal before said reference clock signal until just after the second clock signal after said reference clock signal, and

a signal is present in said third register during the entirety of an interval extending from just before the thirteenth clock signal before said reference clock signal until just after the fourth clock signal before said reference clock signal; and

means for inserting a signal in said first register at a time corresponding to the seventh clock signal before said reference clock signal if said condition of said eighth logic means is true.