Electrically-programmable low-impedance anti-fuse element

• US 4,899,205 A
• Filed: 12/28/1987
• Issued: 02/06/1990
• Est. Priority Date: 05/09/1986
• Status: Expired due to Term

• Current Assignee: Actel Corporation (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Mohsen, Amr M., Hamdy, Esmat Z., McCullum, John L.
• Primary Examiner(s): Larkins, William D.
• Assistant Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US07/137,935
• Time in Patent Office: 771 Days
• Field of Search: 357/23.6, 357/59, 357/54, 357/51
• US Class Current: 257/530
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance anti-fuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath. At least one of the two electrodes of each anti-fuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer. This arsenic will combine with other material and flow into the anti-fuse filament after programmed to form a low resistance controllable anti-fuse link. Circuitry is provided which allows the anti-fuse of the present invention to be programmed by application of a suitable programming voltage to input-output pins of the integrated circuit containing the anti-fuse. Where more than one anti-fuse is to be programmed using the programming voltage applied at the input-output terminals, other additional input-output terminals may serve as address inputs to specify the anti-fuse to be programmed.

In another embodiment of the present invention a programmable read-only memory array comprised of memory cells including an anti-fuse in combination with a single transistor. X-address and Y-address decoder circuits are provided to both program and read the contents of any selected memory cell in the array.

Claims

1. An electrically-programmable, low-impedance anti-fuse element, including:

a p-type semiconductor substrate,

a first electrode comprising a diffusion region in said substrate,

a dielectric layer over said diffusion region, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion,

a second electrode over said dielectric layer,

wherein at least one of said first and said second electrodes is heavily doped or implanted with arsenic such that a high concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode, and a controlled radius conductive filament in said dielectric layer electrically connecting said first and second electrodes.

2. The electrically-programmable, low-impedance anti-fuse element of claim 1, wherein the arsenic doping level is from 1×

10¹⁹ to 1×

10²² atoms/cm³.

3. The electrically-programmable, low-impedance anti-fuse element of claim 1 wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10,000 angstroms.

4. The electrically-programmable, low-impedance anti-fuse element of claim 3 wherein said layer of polysilicon is heavily doped with arsenic such that a high concentration of arsenic exists at the interface between said second electrode and said dielectric layer.

5. The electrically-programmable, low-impedance anti-fuse element of claim 4, wherein the arsenic doping level in said polysilicon is from 1×

10¹⁹ to 1×

10²² atoms/cm³.

6. The electrically-programmable, low-impedance anti-fuse element of claim 1, wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms, and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

7. The electrically-programmable, low-impedance anti-fuse element of claim 1 wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion.

8. The electrically-programmable low-impedance anti-fuse element of claim 6, wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion having a thickness of from 0 to 50 angstroms.

38. A user-programmable read-only-memory array, including:

a plurality of bit lines,

a plurality of word lines, forming intersections with bit lines,

a plurality of memory cells, one of said memory cells located at each of said intersections, each of said memory cells including an electrically-programmable, low-impedance anti-fuse according to any of claims 1-5, 7, 10-11, 13-18, 20, 22-25, 27-29, each of said memory cells further including a transistor having a source, a drain, and a gate, one end of said anti-fuse connected to the one of said bit lines associated with said intersection, the other end of said anti-fuse connected to the drain of said transistor, the source of said transistor being connected to a fixed voltage potential, and the gate of said transistor being connected to the one of said word lines associated with said intersection,

a Y-address decoder having a plurality of Y-address inputs, and a set of outputs, each of said outputs corresponding to one of said word lines in said array, said Y-address decoder operating to activate only one of said word lines for unique combination of said data on said Y-address inputs,

an X-address decoder, having a plurality of X-address inputs, a set of outputs, and a data output, each one of said outputs connected to one of said bit lines, such that only one of said bit lines is connected to said data output when a unique combination of data appears on said X-address inputs,

means for applying a programming voltage to a selected one of said bit lines at a selected time, and,

means for applying said programming voltage to a selected one of said word lines at said selected time.

9. An electrically-programmable, low-impedance anti-fuse element, including:

a p-type semiconductor substrate,

a first electrode comprising a diffusion region in said substrate, said region heavily doped with arsenic such that a high concentration of arsenic exists at the surface of said region,

a dielectric layer over said diffusion region, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, and

a second electrode over said dielectric layer, and a controlled radius conductive filament in said dielectric layer electrically connecting said first and second electrodes.

10. The electrically-programmable low-impedance anti-fuse element of claim 9, wherein the arsenic doping level of said diffusion region is from 1×

10¹⁹ to 1×

10²² atoms/cm³.

11. The electrically-programmable low-impedance anti-fuse element of claim 9 wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10,000 angstroms and is doped with arsenic to a level of from 1×

10¹⁹ to 1×

10²² atoms/cm³ such that a high concentration of arsenic exists at the interface between said second electrode and said dielectric layer.

12. The electrically-programmable low-impedance anti-fuse element of claim 9 wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms, and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

13. The electrically-programmable low-impedance anti-fuse element of claim 9 wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion.

14. The electrically-programmable, low-impedance anti-fuse element of claim 12, wherein said dielectric layer further includes a third silicon dioxide portion having a thickness of from 0 to 50 angstroms.

15. An electrically-programmable, low-impedance anti-fuse element, including:

a semiconductor substrate,

an insulating layer over said semiconductor substrate,

a first electrode formed from a conducting material, over said insulating layer,

a dielectric layer over said first electrode, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, second electrode over said dielectric layer,

wherein at least one of said first and second electrodes is heavily doped with arsenic such that a high concentration of arsenic atoms exists at the interface of said dielectric layer and said heavily doped one of said first or second electrodes and a controlled radius conductive filament in said dielectric layer electrically connecting said first and second electrodes.

16. The electrically-programmable low-impedance anti-fuse element of claim 15 wherein at least one of said first and second electrodes includes a layer of polysilicon heavily doped with arsenic such that a high concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode.

17. The electrically-programmable, low-impedance anti-fuse element of claim 16 wherein said layer of polysilicon has a thickness of from 500 to 10,000 angstrom and is doped with arsenic to a level of from 1×

10.sup.·

to 1×

10²² atoms/cm³.

18. The electrically-programmable, low-impedance anti-fuse element of claim 15 wherein both of said first and second electrodes include a layer of polysilicon having a thickness of from 500 to 10,000 angstroms and doped with arsenic to a level of from 1×

10¹⁹ to 1×

10²² atoms/cm³.

19. The electrically-programmable low-impedance anti-fuse element of claim 15 wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms, and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

20. The electrically-programmable, low-impedance anti-fuse element of claim 15 wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion.

21. The electrically-programmable, low-impedance anti-fuse element of claim 19, wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion having a thickness of from 0 to 50 angstroms.

22. A semiconductor structure disposed in an integrated circuit, including:

a plurality of electrically-programmable low-impedance anti-fuses, each of said anti-fuses including a first electrode formed from a conductive material, a dielectric layer over said first electrode, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, and a second electrode formed of a conductive material over said dielectric layer, wherein at least one of said first and second electrodes is heavily doped with arsenic such that a heavy concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode,

at least one of said electrically-programmable low impedance anti-fuse element including a controlled-radius filament in said dielectric layer electrically connecting said first and second electrodes.

23. The semiconductor structure of claim 22, wherein at least one of said first and second electrodes includes a layer of polysilicon heavily doped with arsenic to a level of 1×

10¹⁹ to 1×

10²² atoms/cm³ having a thickness of from 500 to 10,000 angstroms.

24. The semiconductor structure of claim 22, wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

25. The semiconductor structure of claim 22 further including a third silicon dioxide portion over said second silicon nitride portion in said dielectric layer.

26. The semiconductor structure of claim 24 further including a third silicon dioxide portion over said second silicon nitride portion in said dielectric layer, having a thickness from 0 to 50 angstroms.

27. The semiconductor structure of claim 22, wherein both of said first and said second electrodes of each of said plurality of electrically-programmable low-impedance anti-fuse elements include a layer of polysilicon heavily doped with arsenic such that a high concentration of arsenic atoms exists at the interface between said dielectric layer and each of said first and second electrodes.

28. The semiconductor structure of claim 27 wherein said first and second electrodes include a layer of polysilicon having a thickness of from 500 to 10,000 angstroms doped with arsenic to a level of from 1×

10¹⁹ to 1×

10²² atoms/cm³.

29. The semiconductor structure of claim 22, wherein said controlled-radium filament has a resistance of less than 300 ohms.

37. The semiconductor of any one of claims 22, 23, 24, 26, 28, 29, 30-33, 34-36, further including:

means for applying a programming voltage to said first and second electrodes of selected ones of said anti-fuses from input/output pins of said integrated circuit.

30. A semiconductor structure disposed in an integrated circuit, including:

a plurality of electrically-programmable low-impedance anti-fuses, each of said anti-fuses including a first electrode comprising an n-type diffusion region in a p-type semiconductor substrate of said semiconductor structure, a dielectric layer over said first electrode, said dielectric layer including a first silicon dioxide portion and a second silicon nitride portion over said first silicon dioxide portion, and a second electrode formed of a conductive material over said dielectric layer, wherein at least one of said first and second electrodes is heavily doped with arsenic such that a heavy concentration of arsenic atoms exists at the interface between said dielectric layer and said electrode,

at least one of said electrically-programmable low impedance anti-fuse elements including a controlled-radius filament in said dielectric layer electrically connecting said first and second electrodes.

31. The semiconductor structure of claim 30, wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10,000 angstroms.

32. The semiconductor structure of claim 30, wherein each of said n-type diffusion regions are doped with arsenic to a concentration of from between 1×

10¹⁹ to 1×

10²² atoms/cm³.

33. The semiconductor structure of claim 32, wherein said second electrode includes a layer of polysilicon having a thickness of from 500 to 10,000 angstroms doped with arsenic to a concentration of from 1×

10¹⁹ to 1×

10²² atoms/cm³.

34. The semiconductor structure of claim 30, wherein said first silicon dioxide portion has a thickness of from 20 to 50 angstroms and said second silicon nitride portion has a thickness of from 40 to 100 angstroms.

35. The semiconductor structure of claim 30, further including a third silicon dioxide portion over said second silicon nitride portion in said dielectric layer.

36. The semiconductor structure of claim 34, wherein said dielectric layer further includes a third silicon dioxide portion over said second silicon nitride portion, said third silicon dioxide portion having a thickness of from 0 to 50 angstroms.