Semiconductor integrated circuit device and process for producing the same

• US 4,900,695 A
• Filed: 12/17/1987
• Issued: 02/13/1990
• Est. Priority Date: 12/17/1986
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Itoh, Funikazu, Yamaguchi, HIroshi, Shimase, Akira, Hongo, Mikio, Takahashi, Takahiko, Haraichi, Satoshi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/134,460
• Time in Patent Office: 789 Days
• Field of Search: 437/189, 437/190, 437/192, 437/194, 437/195, 437/197, 437/198, 437/203, 437/288, 148/20, 148/25, 148/26, 148/50, 148/51, 148/90, 148/94, 148/93, 357/71, 357/67
• US Class Current: 438/625
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 21/76894 using a laser, e.g. laser cutting, laser direct writing, laser repair
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 23/5254 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: Y10S 438/94 Laser ablative material removal

Abstract

The present invention relates to a semiconductor integrated circuit device and a process for producing the same. A hole is bored in an insulating film above a portion of a wiring which is to be connected to another wiring by means of a focused ion beam. The inside of the hole and a predetermined region on the insulating film are irradiated with either a laser beam or an ion beam in a metal compound gas to deposit metal in the hole and on said region and a connecting wiring is formed by means of optically pumped CVD. To electrically connect upper- and lower-level wirings in a multilayer wiring structure by a connecting wiring, the connecting wiring is electrically isolated from an intermediate-level wiring through which it extends. The above-described arrangement enables provision of a hole with a focused ion beam and formation of a metal wiring on a selective region by means, for example, optically pumped CVD. Accordingly, it is possible to effect fine machining and electrically connect together wirings inside an LSI after the completion thereof. It is therefore possible to carry out debugging, repair and a defect analysis of the LSI.

Claims

1. A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring is protected by a second insulating film, said method comprising the steps of:

preparing a semiconductor substrate having an integrated circuit formed thereon, said integrated circuit including a semiconductor element having a PN junction, said substrate further having a multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit;

selectively removing successively the second insulating film, the upper-level wiring under said insulating film and the first insulating film under said upper-level wiring in said multilayer wiring structure by machining with a focused ion beam to form a contact hole through which a surface of said lower-level wiring is exposed, said contact hole exposing a surface of the upper-level wiring;

changing a region of said upper-level wiring whose surface is exposed through said contact hole into an insulator; and

forming a connecting wiring by an optically pumped CVD method so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole.

2. A process for producing a semiconductor integrated circuit device according to claim 1, wherein said upper-level wiring is made of a material which contains aluminum as its principal component, said region of said upper-level wiring whose surface is exposed through said contact hole being changed into an insulator by oxidizing said material containing aluminum as its principal component to form alumina.

3. A process for producing a semiconductor integrated circuit device according to claim 1, wherein said optically pumped CVD method is a CVD method that utilizes a laser beam, said connecting wiring being made of one material selected from the group consisting of tungsten (W), molybdenum (Mo), cadmium (Cd) and aluminum (Al).

4. A process for producing a semiconductor integrated circuit device according to claim 1, wherein said connecting wiring is provided with a buffer film as its underlaying conductor which is made of one material selected from the group consisting of chromium (Cr), molybdenum (Mo), tungsten (W) and nickel (Ni).

5. A process for producing a semiconductor integrated circuit device according to claim 1, wherein said substrate is in the form of either a semiconductor wafer which has a plurality of semiconductor integrated circuits formed thereon both lengthwise and crosswise or a semiconductor integrated circuit chip which is formed by dividing said semiconductor wafer into individual semiconductor integrated circuit chips (pellets).

20. A process for producing a semiconductor integrated circuit device according to claim 1, wherein said region of the upper-level wiring that is changed into an insulator includes the surface of the upper-level wiring that is exposed through the contact hole.

23. A process for producing a semiconductor integrated circuit device according to claim 1, wherein said selectively removing is performed at two locations so as to form two contact holes through which surfaces of lower-level wirings are exposed at the two locations;

and said forming a connecting wiring is performed so as to extend over from the inside of each contact hole to a selective region on the surface of said second insulating film.

24. A process for producing a semiconductor integrated circuit device according to claim 23, wherein said forming a connecting wiring is performed so as to electrically connect the lower-level wirings exposed at the two contact holes.

25. A process for producing a semiconductor integrated circuit device according to claim 24, wherein said lower-level wirings include first-level and second-level wirings, the first-level wiring and second-level wiring being formed of different layers of wiring, whereby a connecting wiring interconnecting different layers is provided.

26. A process for producing a semiconductor integrated circuit device according to claim 1, wherein said connecting wiring is provided with a buffer film as its underlying conductor, and wherein said buffer film is made of a semiconductor material containing an active impurity, or of a silicide.

6. A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a first insulating film is interposed between an upper-level wiring and a lower-level wiring and the surface of said upper-level wiring is protected by a second insulating film, said method comprising the steps of:

preparing a semiconductor substrate having an integrated circuit formed thereof, said integrated circuit including a semiconductor element having a PN junction, said substrate further having a multilayer wiring structure formed on its surface, said wiring structure being electrically connected to said integrated circuit;

selectively removing successively the second insulating film in said multilayer wiring structure by machining with a focused ion beam to form a contact hole which exposes the surface of the upper-level wiring in this region;

selectively removing the upper-level wiring the surface of which is exposed through said contact hole by a wet etching process using said second insulating film as an etching mask to form an opening region in said upper-level wiring, said opening region having a larger diameter than that of said contact hole;

selectively removing said first insulating film the surface of which is exposed through said contact hole by machining with a focused ion beam to form an opening portion which exposes the surface of said lower-level wiring in this region; and

forming a connecting wiring by an optically pumped CVD method so as to extend over from the inside of said contact hole to a selective region on the surface of said second insulating film, said connecting wiring being electrically connected to said lower-level wiring the surface of which is exposed through said contact hole.

7. A process for producing a semiconductor integrated circuit device according to claim 6, wherein said upper-level wiring is made of a material which contains aluminum at its principal component.

8. A process for producing a semiconductor integrated circuit device according to claim 6, wherein said optically pumped CVD method is a CVD method that utilizes a laser beam, said connecting wiring being made of one material selected from the group consisting of tungsten (W), molybdenum (Mo), cadmium (Cd) and aluminum (Al).

9. A process for producing a semiconductor integrated circuit device according to claim 6, wherein said connecting wiring is provided with a buffer film as its underlaying conductor which is made of one material selected from the group consisting of chromium (Cr), molybdenum (Mo), tungsten (W) and nickel (Ni).

10. A process for producing a semiconductor integrated circuit device according to claim 6, wherein said substrate is in the form of either a semiconductor wafer which has a plurality of semiconductor integrated circuits formed thereon both lengthwise and crosswise or a semiconductor integrated circuit chip which is formed by dividing said semiconductor wafer into individual semiconductor integrated circuit chips (pellets).

27. A process for producing a semiconductor integrated circuit device according to claim 6, wherein said wet etching process is performed using, as the etchant, a solution of phosphoric acid, glacial acetic acid, nitric acid and water.

11. A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a plurality of layers of wirings are isolated from each other by respective insulating films and a connecting wiring is connected to a lower-level wiring through a contact hole provided so as to extend through an upper-level wiring, said process comprising the steps of:

forming said contact hole by irradiation with an ion beam, said contact hole exposing a surface of the upper-level wiring;

changing a portion of said upper-level wiring whose surface is exposed through said contact hole into an insulator; and

forming said connecting wiring by laser CVD.

12. A process for producing a semiconductor integrated circuit device according to claim 11, wherein said multilayer wiring structure is a double-layer wiring structure.

13. A process for producing a semiconductor integrated circuit device according to claim 11, wherein said wirings are aluminum wirings.

14. A process for producing a semiconductor integrated circuit device according to claim 11, wherein said insulator is alumina.

15. A process for producing a semiconductor integrated circuit device according to claim 14, wherein said alumina is formed by either anodizing or oxygen plasma oxidation.

16. A process for producing a semiconductor integrated circuit device according to claim 11, wherein said connecting wiring is defined by a molybdenum, tungsten, cadmium or aluminum film.

17. A process for producing a semiconductor integrated circuit device according to claim 11, wherein said connecting wiring is formed by laser CVD employing an organic metal compound.

21. A process for producing a semiconductor integrated circuit device according to claim 11, wherein said portion of the upper-level wiring that is turned into the insulator includes the surface of the upper-level wiring that is exposed through the contact hole.

22. A process for producing a semiconductor integrated circuit device according to claim 11, wherein the upper-level wiring is made of a refractory material, and said changing is performed by a heat treatment while irradiating the exposed surface of the upper-level wiring with ozone.

29. A process for producing a semiconductor integrated circuit device according to claim 11, wherein two contact hole, at spaced locations, are provided to extend through the upper-level wiring, each contact hole exposing a surface of the upper-level wiring;

and said changing, and said forming said connecting wiring, steps are performed for each of said contact holes.

30. A process for producing a semiconductor integrated circuit device according to claim 29, wherein the step of forming said connecting wiring is performed so as to electrically connect lower-level wirings through said two contact holes.

18. A process for producing a semiconductor integrated circuit device wherein holes are bored in an upper-level insulating film at a portion thereof where contact holes are to be provided by machining with an energy beam and then the insides of these holes and the region therebetween are irradiated with a laser or focused ion beam in an atmosphere containing a metal compound gas to deposit a metal on the irradiated regions, thereby forming a metal film between wirings and thus electrically connecting together these wirings, wherein the improvement comprises notching a portion of the upper-level wiring at which the metal is deposited to form a notch, the notch being formed so as to extend completely through the upper-level wiring at a location around the contact holes, thereby electrically isolating said portion from another portion of the upper-level wiring.

19. A process for producing a semiconductor integrated circuit device according to claim 18, wherein said notching is carried out with an energy beam such as a focused ion beam in such a manner that scanning for machining is started from an edge portion of a step of a protective film provided on said upper-level wiring and the point of starting the scanning is shifted toward the lower side of the step as the depth of machining increases, the shift of the starting point being repeated until the bottom surface of the machined groove is coincident with the lower portion of said protective film.

28. A process for producing a semiconductor integrated circuit device according to claim 18, wherein said energy beam is a focused ion beam.

31. A process for producing a semiconductor integrated circuit device having a multilayer wiring structure in which a plurality of layers of wirings are isolated from each other by respective insulating films and a connecting wiring is connected to a lower-level wiring through a contact hole provided so as to extend through an upper-level wiring, said process comprising the steps of:

forming said contact hole by irradiation with a focused ion beam, so as to expose the lower-level wiring, the contact hole being formed so that upper portions of the hole are larger than lower portions; and

forming said connecting wiring by irradiating the contact hole with a focused laser beam or focused ion beam, in an atmosphere of a metal compound gas, to deposit a metal of said connecting wiring.