Frequency synthesizer with an interface controller and buffer memory

• US 4,901,036 A
• Filed: 06/29/1989
• Issued: 02/13/1990
• Est. Priority Date: 06/29/1989
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Rivas, Mario A., Tahernia, Omid, Herold, Barry W., Davis, Walter L.
• Primary Examiner(s): Laroche, Eugene R.
• Assistant Examiner(s): Pascal, Robert J.
• Application Number:
  US07/372,997
• Time in Patent Office: 229 Days
• Field of Search: 331/1 A, 331/23, 331/25, 358/191.1, 455/165, 455/183, 455/260, 307/529
• US Class Current: 331/25
• CPC Class Codes: H03J 5/0281 the digital values being held in an auxiliary non erasable memory

Abstract

A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

Claims

1. A frequency synthesizer including at least one phase lock loop (PLL) circuit operationally characterized by a central controller to generate a synthesized channel frequency signal, said PLL circuit including at least one storage register dynamically programmable with data words which characterize the operation of said PLL circuit in generating said synthesized channel frequency signal, said frequency synthesizer comprising:

an interface controller coupled between said central controller and said at least one storage register of said PLL circuit and operative to receive operational code words and data words from said central controller; and

a buffer memory coupled to said interface controller for storing a plurality of data words for characterizing the operation of said phase lock loop, said interface controller responsive to said operational code words received from said central controller to direct a transfer of data words between said central controller, said at least one storage register and said buffer memory.

2. The frequency synthesizer in accordance with claim 1 wherein the interface controller includes:

first means selectively operative to couple the central controller to the at least one storage register and to control the transfer of a data word therebetween;

second means selectively operative to couple the central controller to the buffer memory and to control the transfer of a data word therebetween;

third means selectively operative to couple the buffer memory to the at least one storage register and to control the transfer of a data word therebetween; and

means for decoding an operational code word received from the central controller and for selecting one of said first, second and third means to perform its specified operation based on said decoded operational code word.

3. The frequency synthesizer in accordance with claim 2 wherein the operational code words and data words are transferred in a serial format among the central controller, the interface controller, the buffer memory and the at least one storage register.

4. The frequency synthesizer in accordance with claim 3 wherein the interface controller includes four ports for coupling to the central controller--first port for receiving from the central controller a select signal, second port for receiving from the central controller a clock signal which synchronizes the serial transfer of operational code words and data words, third port for receiving operational code words and data words from the central controller in a serial format, and fourth port for sending data words to the central controller in a serial format.

5. The frequency synthesizer in accordance with claim 4 wherein the interface controller includes means for selectively converting the third port into a bidirectional serial word transfer port for both sending and receiving words of a serial format.

6. The frequency synthesizer in accordance with claim 3 wherein the interface controller includes three ports for coupling to the central controller--first port for receiving a select signal, second port for receiving a clock signal which synchronizes the serial transfer of operational code words and data words, and third port for bidirectionally sending and receiving words of a serial format respectively to and from the central controller.

7. The frequency synthesizer in accordance with claim 3 wherein the decoding means includes:

a shift register for receiving from the central controller an operational code word in a serial format and converting the operational code word to a parallel format;

a latch register coupled to said shift register for storing the parallel formatted operational code word; and

means for decoding the operational code word stored in said latch register and for selecting one of the first, second and third means to perform its specified operation based on said decoded operational code word.

8. The frequency synthesizer in accordance with claim 7 wherein the interface controller includes means for receiving a select signal and a clock signal from the central controller;

wherein the shift register is synchronized by said clock signal to serially receive an operational code word from the central controller; and

wherein the latch register is governed by the select signal to preset an operational code word into the latch register, which preset code word being decoded to render a coupling between the central controller and the shift register for synchronous reception of the operational code word.

9. The frequency synthesizer in accordance with claim 1 including means for generating a reference frequency signal for the PLL circuit in accordance with a programmed, characterization, and an associated storage register dynamically programmable with a data word which characterizes the operation of said generating means;

and wherein the interface controller is coupled to said associated storage register and is responsive to an operational code word received from the central controller to direct a transfer of a data word between the central controller and said associated storage register.

10. The frequency synthesizer in accordance with claim 1 including means for generating a loop bias control signal for the PLL circuit in accordance with a programmed characterization, and an associated storage register dynamically programmable with a data word which characterizes the operation of said generating means;

and wherein the interface controller is coupled to said associated storage register and is responsive to an operational code word received from the central controller to direct a transfer of a data word between the central controller and said associated storage register.

11. A frequency synthesizer including at least one phase lock loop (PLL) circuit operationally characterized by a central controller to generate a synthesized channel frequency signal, said PLL circuit including at least one storage register dynamically programmable with data words which characterize the operation of said PLL circuit in generating said synthesized channel frequency signal, said frequency synthesizer comprising:

an interface controller operative to receive operational code words, corresponding data words, and characterization data words from the central controller; and

a buffer memory coupled to said interface controller for storing a plurality of characterization data words in a corresponding plurality of registers, each such data word corresponding to a unique characterization of operation of said PLL circuit in generating said synthesized channel frequency signal, said interface controller responsive to a first operational code word and corresponding first data word to transfer a characterization data word from said central controller to said buffer memory for storage in a register uniquely corresponding to the code of said first data word, and responsive to a second operational code word and corresponding second data word to transfer a characterization data word from a register of said buffer memory corresponding uniquely to the code of the second data word to said at least one storage register of said PLL circuit, whereby said at least one storage register of the PLL circuit is dynamically programmed with the transferred characterization data word from the buffer memory.

12. The frequency synthesizer in accordance with claim 11 wherein the buffer memory includes a shift register which is operative to convert a data word from a serial format to a parallel format for storage in a register of the buffer memory;

and wherein the interface controller includes;

means for receiving a clock signal from the central controller; and

means responsive to the first operational code word and governed by said clock signal of the central controller to shift a characterization data word of serial format into the shift register of the buffer memory from the central controller.

13. The frequency synthesizer in accordance with claim 11 wherein the buffer memory includes a first shift register which is operative to convert a data word from a parallel format to a serial format;

wherein the at least one register of the PLL circuit includes a second shift register which is operative to convert a data word from a serial format to a parallel format; and

wherein the interface controller includes means responsive to the second operational code word to transfer the characterization data word, accessed from the buffer memory by the corresponding second data word, to the first shift register in parallel and, governed by an internal clock signal, generated independent of the central controller, to shift the characterization data word serially from the first shift register to the second shift register.

14. The frequency synthesizer in accordance with claim 13 wherein the at least one storage register of the PLL circuit includes a latch register operative, upon command, to transfer in a parallel format the characterization data word of the second shift register to the PLL circuit to characterize the operation thereof in generating the synthesized channel frequency signal;

and wherein the interface controller includes means for receiving a select signal from the central controller, and means responsive to the select signal to operate said latch register.

15. The frequency synthesizer in accordance with claim 13 including a second PLL circuit operationally characterized by the central controller to generate another synthesized channel frequency signal, said second PLL circuit including a third shift register operative to convert a data word from a serial format to a parallel format;

wherein the interface controller includes means responsive to a third operational code word to transfer a characterization data word in parallel from a register of the buffer memory corresponding to the third operational code word to the first shift register and, governed by the internal clock signal, to shift the characterization data word serially from the first shift register to the third shift register of the second PLL circuit.

16. The frequency synthesizer in accordance with claim 15 wherein the second PLL circuit includes a latch register operative, upon command, to transfer in a parallel format the characterization data word of the third shift register to the second PLL circuit to characterize the operation thereof in generating the other synthesized channel frequency signal;

and wherein the interface controller includes means for receiving a select signal from the central controller, and means responsive to the select signal to operate said latch register.

17. The frequency synthesizer in accordance with claim 15 wherein the interface controller includes means responsive to a fourth operational code word and corresponding fourth data word to transfer a first characterization data word in parallel from a register of the buffer memory corresponding to the fourth operational code word to the first shift register and, governed by the internal clock signal, to shift the first characterization data word serially from the first shift register to the second shift register, and upon completion of said shifting operation, to transfer a second characterization data word in parallel from a register of the buffer memory corresponding to the code of the fourth data word to the first shift register and, governed by the internal clock signal, to shift the second characterization data word serially from the first shift register to the second shift register while concurrently shifting the first characterization data word serially from the second shift register to the third shift register, whereby, upon completion of the latter shifting operation, the first characterization data word is stored in the third shift register of the second PLL circuit and the second characterization data word is stored in the second shift register of the PLL circuit.

18. The frequency synthesizer in accordance with claim 17 wherein the PLL circuit includes a first latch circuit operative, upon command, to transfer the characterization data word of the second shift register to the PLL circuit to characterize the operation thereof in generating the synthesized channel frequency signal;

wherein the second PLL circuit includes a second latch circuit operative, upon command, to transfer the characterization data word of the third shift register to the second PLL circuit to characterize the operation thereof in generating the other synthesized channel frequency signal; and

wherein the interface controller includes means for receiving a select signal from the central controller, and means responsive to the select signal to operate concurrently the first and second latch registers.

19. The frequency synthesizer in accordance with claim 11 wherein the interface controller includes four ports for coupling to the central controller--first port for receiving from the central controller a select signal, second port for receiving from the central controller a clock signal which synchronizes the serial transfer of operational code words and data words, third port for receiving operation code words and data words from the central controller in a serial format, and fourth port for sending data words to the central controller in a serial format.

20. The frequency synthesizer in accordance with claim 19 wherein the interface controller includes means for selectively converting the third port into a bidirectional serial word transfer port for both sending and receiving words of a serial format.

21. The frequency synthesizer in accordance with claim 11 wherein the interface controller includes three ports for coupling to the central controller--first port for receiving a select signal, second port for receiving a clock signal which synchronizes the serial transfer of operational code words and data words, and third port for bidirectionally sending and receiving words of a serial format respectively to and from the central controller.

22. A frequency synthesizer including a plurality of phase lock loop (PLL) circuits, each operationally characterized by a central controller to generate a corresponding synthesized channel frequency signal, each including a storage register dynamically programmable with data words which characterize the operation of its corresponding PLL circuit in generating its synthesized channel frequency signal, said frequency synthesizer comprising:

an interface controller operative to receive operational code words, corresponding data words, and characterization data words from the central controller; and

a buffer memory coupled to said interface controller for storing a plurality of characterization data words in a corresponding plurality of registers, each such data word corresponding to a unique characterization of operation of a PLL circuit in generating its synthesized channel frequency signal, said interface controller responsive to an operational code word and corresponding data word to direct a transfer of a characterization data word from a selected register of said buffer memory to the storage register of a selected one of said plurality of PLL circuits.

23. The frequency synthesizer in accordance with claim 22 wherein the interface controller directs the transfer of a characterization data word from the buffer memory to a selected one of said plurality of PLL circuits autonomously in response to an operational code word and corresponding data word received from the central controller.

24. The frequency synthesizer in accordance with claim 22 wherein the interface controller includes means for accessing a characterization data word from a register of the buffer memory based on the code of a corresponding data word for transfer to a PLL circuit.

25. The frequency synthesizer in accordance with claim 22 wherein the interface controller includes means for accessing a characterization data word from a register of the buffer memory based on the code of an operational code word for transfer to a PLL circuit.

26. The frequency synthesizer in accordance with claim 22 wherein the interface controller includes means responsive to a single operational code word and single corresponding data word to direct a transfer of a plurality of characterization data words from selected corresponding registers of the buffer memory to the storage registers of a selected corresponding plurality of PLL circuits.