Sigma-delta modulator for D-to-A converter
First Claim
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1. Digital-to-analog conversion means comprising:
- a signal input terminal for applying binary samples at a first rate;
sampled data sigma-delta modulator means, coupled to said signal input terminal, for resampling said binary samples to produce samples more coarsely quantized than said binary samples and at a rate greater than said first rate;
sample conversion means for converting said coarsely quantized samples into sequences of pulses, the number of pulses in a sequence being determined by amplitude values represented by said coarsely quantized samples; and
analog means for integrating/averaging said pulse sequences.
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Abstract
A digital-to-analog converter includes a sampled data sigma-delta modulator to resample and coarsely quantize the digital samples to be converted. The coarsely quantized samples are converted to sequences of pulses which are applied to a pulse sensitive analog integrator to develop analog representations of the digital signal.
37 Citations
15 Claims
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1. Digital-to-analog conversion means comprising:
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a signal input terminal for applying binary samples at a first rate; sampled data sigma-delta modulator means, coupled to said signal input terminal, for resampling said binary samples to produce samples more coarsely quantized than said binary samples and at a rate greater than said first rate; sample conversion means for converting said coarsely quantized samples into sequences of pulses, the number of pulses in a sequence being determined by amplitude values represented by said coarsely quantized samples; and analog means for integrating/averaging said pulse sequences.
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2. Digital-to-analog conversion means comprising:
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a signal input terminal for applying bit-serial binary samples at a first sample rate; sampled data sigma-delta modulator means, coupled to said signal input terminal, for resampling said bit-serial binary samples to produce samples more coarsely quantized than said bit-serial binary samples and at a greater rate than said first sample rate, said sigma-delta modulator including a plurality of one-bit serial accumulators interconnected to operate in a pipelined manner; integrating/averaging means coupled to said sigma-delta modulator for generating an analog signal from said coarsely quantized samples. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10)
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11. A pipelined sigma-delta modulator, comprising:
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a bit-serial input terminal for receiving bit-serial data; a plurality of first cells each cell including an adder having first and second data input terminals, one bit carry input and output terminals and a one bit sum output terminal; delay means coupled between said sum output terminal and said first input terminal; a serial data input terminal; and means including storage means coupled to said serial data input terminal for providing data to said second input terminal; means for parallel connecting said plurality of first cells wherein said first cells are ordinally numbered and the carry output terminal of respective cells are coupled to the carry input terminal of the next higher ordinally numbered cell; a plurality of second cells each of which includes; first and second adders each including first and second data input terminals, carry input and output terminals and a sum output terminal; delay means coupled between the sum output and first data input terminals of the first adder; a data output terminal coupled to the sum output terminal of said first adder; means for coupling the sum output terminal of the second adder to the second data input terminal of the first adder; a quantized data input terminal coupled to the first data input terminal of the second adder; a serial data input terminal; and means including storage means coupled to said serial data input terminal for providing data to said second input terminal of said second adder; means for parallel connecting said plurality of second cells wherein said second cells are ordinally numbered and the carry output terminals of said first and second adders of respective second cells are respectively coupled to the carry input terminals of the first and second adders of the next higher ordinally numbered cell; means for coupling the carry output terminal of the highest ordinally numbered first cell to the carry input terminal of the first adder of the lowest ordinally numbered second cell; means for coupling the data input terminals of said first and second cells to said bit-serial input terminal including means for coupling bits of said bit-serial signal of successively increasing significance respectively to cells of successively higher ordinal numbering. - View Dependent Claims (12, 13)
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14. Bit-serial processing apparatus comprising:
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a bit-serial input terminal; a first plurality of ordinally numbered cells, each cell including; a one bit accumulator having a data input, a carry input and a carry output terminal; means including storage means, having an input terminal and having an output terminal coupled to said data input terminal, for coupling signal to said accumulator; means for interconnecting said first plurality of cells, wherein said carry output terminal of respective cells is coupled to the carry input terminal of the next higher ordinally numbered cell; a second plurality of ordinally numbered cells, each cell including; a one bit accumulator having a data input, a carry input, a data output and a carry output terminal; combining means having an output coupled to the data input terminal of said accumulator, having first and second data input terminals, a carry input and a carry output terminal for arithmetically combining values applied to its first and second data input and carry input terminals; means, including storage means, having an output coupled to the first data input terminal of said combining means, and having an input coupled to said bit-serial input terminal for coupling signal to said combining means; means for interconnecting said second plurality of cells wherein the carry output terminals of said accumulator and combining means of respective cells are respectively coupled to the carry input terminals of the accumulator and combining means of the next higher ordinally numbered cell; means for coupling the carry output terminal of the highest ordinally numbered cell of said first plurality of cells to the carry input terminal of the accumulator of the lowest ordinally numbered cell of said second plurality of cells; and means for applying signal to the second data input terminals of the combining means of ones of said second plurality of cells. - View Dependent Claims (15)
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Specification