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Semiconductor memory

  • US 4,901,128 A
  • Filed: 11/24/1986
  • Issued: 02/13/1990
  • Est. Priority Date: 11/04/1982
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each memory cell including an insulated-gate field-effect transistor and a capacitor with a data storage portion formed on a semiconductor surface region having a first conductivity type, wherein said insulated-gate field-effect transistor comprises:

  • a gate electrode electrically connected to one of the plurality of word lines,a source and drain provided in the semiconductor surface region, one of the plurality of bit lines being connected to the drain or source of the insulated-gate field-effect transistor, anda gate insulation film provided between the semiconductor surface region and the gate electrode, the gate insulation film being formed less than 50 nm; and

    wherein said capacitor comprises;

    a groove formed into the semiconductor surface region, wherein a depth of the groove is more than 1 μ

    m, wherein the depth of the groove is greater than a distance between inner walls of the grooves, and wherein the semiconductor surface region surrounding the groove acts as a first electrode,a capacitor insulation film formed on a surface of the groove, wherein the capacitor insulation film comprises a composite film of SiO2 and Si3 N4, anda second electrode formed in the groove over the capacitor insulation film, the second electrode being connected to the source or drain of the insulated-gate field-effect transistor, wherein the second electrode comprises a polycrystalline silicon, and wherein the groove is filled with the second electrode,wherein an individual groove is provided for forming the capacitor for each memory cell.

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