Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio

• US 4,901,267 A
• Filed: 03/14/1988
• Issued: 02/13/1990
• Est. Priority Date: 03/14/1988
• Status: Expired due to Term

• Current Assignee: Weitek Corp.
• Original Assignee: Weitek Corp.
• Inventors: Birman, Mark, Chu, George K., Ware, Fred A., Halim, Selfia
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US07/167,802
• Time in Patent Office: 701 Days
• Field of Search: 364/736, 364/748, 364/754, 364/761
• US Class Current: 708/513
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

The present invention optimizes the number and ratio of cycles required among the divide/square root unit, multiplier unit and ALU. An intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers. The multiplier can then be adjusted for either two-cycle latency mode (for optimizing double-precision multiplies) or three-cycle latency mode (for optimizing single-precision multiplies). A separate divide clock is used for the divide/square root unit, and is synchronized with the multiplier cycle clock on input and output. This allows the divide time to be optimized so that it requires fewer clock cycles when a longer multiplier clock cycle time is used.

Claims

1. In a circuit having a multiplier, an arithmetic logic unit and means for providing a primary cycle clock, said multiplier having a first stage including an input register, a second stage including a multiplexer coupled to said input register and a multiplier array coupled to said multiplexer, and a third stage including an output register or latch coupled to said multiplier array, the improvement comprising:

a latch having an input coupled to an output of said multiplier array;

a first data bus coupling an output of said latch to an input of said multiplexer;

a second data bus coupling said multiplier array directly to said output register; and

means for selectively providing said primary cycle clock or a fraction of said primary cycle clock to a clock input of said latch.

2. In a circuit having a multiplier unit and a divide and square root unit, both said units being coupled to receive operands from a multiplier circuit for selecting operands, said multiplier receiving a system clock signal from a clock circuit, the improvement comprising:

means, coupled to said clock circuit, for providing a divide clock signal to said divide and square root unit, said divide clock signal having a frequency which is an integral multiple, other than one, of a frequency of said system clock signal;

means, coupled to an input of said divide and square root unit, for synchronizing a data input of said divide and square root unit to said system clock signal and said divide clock signal; and

means, coupled to an output of said divide and square root unit, for synchronizing a data output of said divide and square root unit to said system clock signal and said divide clock signal.

3. The circuit of claim 2 further comprising:

means for generating a divide start signal for initiating a divide or square root operation;

said means for synchronizing a data input comprising an AND-gate coupled to receive said system clock signal and said divide start signal and a register or latch coupled to receive an output of said AND-gate and having a clock input coupled to receive said divide clock signal.

4. The circuit of claim 2 wherein said divide and square root unit includes means for generating a divide stop signal to indicate the end of a divide or square root operation, said means for synchronizing a data output comprising a first register or latch receiving said divide stop signal as an input and having a clock input coupled to receive said divide clock signal and a second register or latch having an input coupled to receive an output of said first register or latch and having a clock input coupled to receive said system clock signal.

5. In a circuit having a multiplier, an arithmetic logic unit, a divide and square root unit and means for providing a primary cycle clock, said multiplier having a first stage including an input register, a second stage including a multiplexer coupled to said input register and a multiplexer array coupled to said multiplexer, and a third stage including man output register or latch coupled to said multiplier array, the improvement comprising:

a latch having an input coupled to an output of said multiplier array;

a first data bus coupling an output of said latch to an input of said multiplexer;

a second data bus coupling said multiplier array directly to said output register;

means, coupled to said means for providing a primary cycle clock, for selectively providing said primary cycle clock or a fraction of said primary cycle clock to a clock input of said latch;

means for providing a divide clock to said divide and square root unit, said divide clock having a frequency which is an integral multiple of a frequency of said primary cycle clock;

means for synchronizing a data input of said divide and square root unit to said primary cycle clock and said divide clock; and

means for synchronizing a data output of said divide and square root unit to said primary cycle clock and said divide clock.

6. A method for adjusting the latency mode of a multiplier circuit having a first stage including an input register, a second stage including a multiplexer coupled to said input register and a multiplier array coupled to said multiplexer, and a third stage including an output register or latch coupled to said multiplier array, comprising the steps of:

providing a latch having an input coupled to an output of said multiplier array;

providing a first data bus coupling an output of said latch to an input of said multiplexer;

providing a second data bus coupling said multiplier array directly to said output register; and

providing one of a primary clock signal or a fraction of said primary clock signal to a clock input of said latch.

7. A method for providing a selectable frequency divide clock in a circuit having a multiplier unit and a divide and square root unit, both said units being coupled to a multiplexer circuit for selecting operands, said multiplier receiving a system clock from a clock circuit, comprising the steps of:

providing a divide clock to said divide and square root unit, said divide clock having a frequency which is an integral multiple, other than one, of a frequency of said system clock;

synchronizing a data input of said divide and square root unit to said system clock and said divide clock; and

synchronizing a data output of said divide and square root unit to said system clock and said divide clock.