Analog data acquisition apparatus and method provided with electro-optical isolation

• US 4,901,275 A
• Filed: 09/04/1987
• Issued: 02/13/1990
• Est. Priority Date: 12/18/1986
• Status: Expired due to Fees

• Current Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Original Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Inventors: Vine, David, Hardie, Ian
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Munteanu-R., Florin
• Application Number:
  US07/093,253
• Time in Patent Office: 893 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/485, 364/486, 364/487, 324/78 D, 324/79 D
• US Class Current: 710/69
• CPC Class Codes: G06F 3/05 Digital input using the sampling of an analogue quantity at regular intervals of time , input from a/d converter or output to d/a converter

Abstract

A unit for providing an interface between analog input signals and a digital data processing system bus includes a plurality of analog input channels, sample-and-hold circuits, and an analog-to-digital converter. An optical isolation circuit couples the output of the analog-to-digital converter to a dual-port RAM. The gain of each analog input channel is programmable, as is the address of each input channel in the RAM. Thus the channels can be read in any desired order, and different input voltage ranges can be programmed for each channel. The RAM can be read by an external data processing system via a digital system bus.

Claims

1. A data acquisition interface unit for processing a plurality of analog data input signals for use by an external digital data processing system comprising:

(a) circuit means for selecting, setting a gain on and digitizing a selected one of said plurality of analog input signals, said circuit means including;

(i) multi-channel multiplexer means comprising 0-63 input channels for receiving said plurality of analog data input signals,

(ii) channel address logic circuit means coupled to said multi-channel multiplexer means for enabling selection of a particular analog signal to be processed,

(iii) channel gain circuit coupled to a programmable gain amplifier for enabling said setting a gain on said particular analog signal to be processed, said programmable gain amplifier also being coupled to said multi-channel multiplexer means, and

(iv) analog-to-digital converter coupled to said programmable gain amplifier via a sample-and-hold circuit, said analog-to-digital converter digitizing said particular analog signal to be processed;

(b) parallel-to-serial-to-parallel optical coupling circuitry means coupled to said circuit means for processing said digitized analog signal;

(c) memory means coupled to said parallel-to-serial-to-parallel optical coupling means for storing said processed digital signal, said memory means also storing a channel scan list consisting of channel order information relating to selection of said 0-63 input channels to be processed and gain information relating to a gain to be applied on analog signals received on said 0-63 input channels prior to being digitized;

input/output data bus means coupled to said memory means for coupling said interface unit to said external data processing system; and

local data bus coupled to said input/output data bus means and to said memory means for receiving and transferring interrupt, status, channel address, and control information generated by interrupt vector logic, status register, channel address generator and control register circuitry, respectively, to said memory means via a memory address bus and to said circuit means via a memory data bus coupled to said parallel-to-serial-to-parallel optical coupling means.

2. A method of interfacing an analog input data signal to a digital data processing unit, said method comprising the steps of:

(a) providing a data acquisition interface unit, said unit comprising;

(i) circuit means for selecting, setting a gain on, and digitizing a, selected one of a plurality of analog input signals, said circuit means including;

multi-channel multiplexer means comprising 0-63 input channels for receiving said plurality of analog data input signals,

channel address logic circuit means coupled to said multi-channel multiplexer means for enabling selection of a particular analog signal to be processed,

channel gain circuit coupled to a programmable gain amplifier for enabling said setting a gain on said particular analog signal to be processed, said programmable gain amplifier also being coupled to said multi-channel multiplexer means, and

analog-to-digital converter coupled to said programmable gain amplifier via a sample-and-hold circuit, said analog-to-digital converter digitizing said particular analog signal to be processed,

(ii) parallel-to-serial-to-parallel, optical coupling circuitry means coupled to said circuit means for processing said digitized analog signals,

(iii) memory means coupled to said parallel-to-serial-to-parallel optical coupling means for storing digital data including a processed digital signal, control data, channel scan and gain information, said channel scan information consisting of channel order information relating to selection of said 0-63 input channels to be processed and said gain information relating to a gain to be applied on analog signals received on said 0-63 input channels prior to being digitized,

(iv) system input/output data bus means coupled to said memory means for coupling said interface unit to said external data processing system and communicating digital information, and

(v) local data bus coupled to said input/output data bus means and to said memory means for receiving and transferring interrupt, status, channel address, and control information generated by interrupt vector logic, status register, channel address generator and control register circuitry, respectively, to said memory means via a memory address bus and to said circuit means via a memory data bus coupled to said parallel-to-serial-to-parallel optical coupling means;

(b) accessing said channel scan and said gain information for selecting and setting a gain on a particular one of said plurality of input analog data signals received on said 0-63 input channels;

(c) digitizing said selected one analog data signal using said analog-to-digital converter;

(d) processing said digitized analog data signal via said optical coupling circuitry means;

(e) mapping and storing said processed digitized analog data signal to said memory means;

(f) performing I/O data communications through said system input/output data bus means, including transferring said stored digitized analog data signal; and

(g) controlling input channel address/gain selection via said local data bus and said system input/output data bus means.