Efficient maximum-likelihood decoder for the golay (24,12) code
First Claim
1. An efficient maximum likelihood decoder for the Golay (24,12) code comprising:
- precomputational circuit means for receiving a dimensional vector (X) to be decoded,register means comprising a plurality of sets of storage registers for dividing said dimensional vector information into sets of information,bit serial adder means coupled to said individual sets of said registers for producing precomputed SGK values representative of said sets of information,random access (RAM) storage means for storing said SGK values,inner product circuit means comprising a plurality of processing elements,each of said processing elements being coupled to a part of said RAM storage means representative of sets of said SGK values,means for addressing and sequentially reading said precomputed SGK values out of said random access storage means into said inner product circuit means,means for comparing said SGK values and for determining a minimum SGK values and the subcode values for the SGK values,means for determining the sign of the SGK subcode values,means for calculating and selecting the largest inner product values for said subcode values,select means for determining the single subcode value whose inner product with the received dimensional vector (X) is the largest, andmeans for presenting said subcode value as information bits associated with said subcode value to a utilization device.
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Abstract
A novel maximum likeihood decoder for the Golay (24,12) code is provided. Instead of decoding the received dimensional vector (X) is a systolic array, the vector is mapped into a (24,5) subcode with an index 128 which is easily decoded. The decoder employs a plurality of precomputational circuits cooperating with a similar plurality of inner product circuits which compute the 128 inner product values and select the maximum inner product value from each inner product circuit. The maximum inner product value from each circuit is loaded into a select logic circuit for selecting the maximum inner product value and its corresponding code word closest to the received vector (X).
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Citations
18 Claims
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1. An efficient maximum likelihood decoder for the Golay (24,12) code comprising:
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precomputational circuit means for receiving a dimensional vector (X) to be decoded, register means comprising a plurality of sets of storage registers for dividing said dimensional vector information into sets of information, bit serial adder means coupled to said individual sets of said registers for producing precomputed SGK values representative of said sets of information, random access (RAM) storage means for storing said SGK values, inner product circuit means comprising a plurality of processing elements, each of said processing elements being coupled to a part of said RAM storage means representative of sets of said SGK values, means for addressing and sequentially reading said precomputed SGK values out of said random access storage means into said inner product circuit means, means for comparing said SGK values and for determining a minimum SGK values and the subcode values for the SGK values, means for determining the sign of the SGK subcode values, means for calculating and selecting the largest inner product values for said subcode values, select means for determining the single subcode value whose inner product with the received dimensional vector (X) is the largest, and means for presenting said subcode value as information bits associated with said subcode value to a utilization device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification