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Gated architecture for computer vision machine

  • US 4,901,360 A
  • Filed: 10/23/1987
  • Issued: 02/13/1990
  • Est. Priority Date: 10/23/1987
  • Status: Expired due to Term
First Claim
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1. A computer architecture for performing iconic and symbolic operations, said architecture comprising:

  • an array of substantially identical processing elements (PE) arranged in horizontal rows and vertical columns, each PE having electrically conductive lines running in the North, South, East and West directions connected to neighboring PEs in those directions, respectively;

    the North and South lines being connected together to form a vertical line, with the East and West lines being connected together to form a horizontal line;

    each PE having a node with a programmable voltage level thereon representing a given logical state of the PE, the array being arranged so that said logical state on the node can be simultaneously shared between PEs which are connected together;

    a vertical gate connected between the vertical line and the node in each PE to thereby permit selective connection of PE nodes in a column together;

    a horizontal gate connected between the horizontal line and the node in each PE to thereby permit selective connection of PE nodes in a row together;

    control means for opening and closing the gates; and

    memory means in each PE coupled to said node for storing a some/none result related to whether some or none of the nodes of the connected PEs are in a given logical state.

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