Gated architecture for computer vision machine

• US 4,901,360 A
• Filed: 10/23/1987
• Issued: 02/13/1990
• Est. Priority Date: 10/23/1987
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (AT&T, Inc.)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Nash, James G., Shu, David B.
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Couso, Jose L.
• Application Number:
  US07/113,084
• Time in Patent Office: 844 Days
• Field of Search: 382/27, 382/34, 382/41, 382/49, 364/131, 364/133, 364/229, 364/229.41, 364/229.5
• US Class Current: 382/303
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A computer architecture 10 for performing iconic and symbolic operations on image data is disclosed. Three levels of processing elements (CAAPP, ICP, GPPA) are disclosed. The processing elements in the lowest level (CAAPP) are provided with a plurality of controllable gates (N, S, E, W, H, V, NW, NE) that are used to selectively connect together processing elements in that level. In such manner, certain algorithms such as the minimum spanning tree algorithm can be efficiently performed.

Claims

1. A computer architecture for performing iconic and symbolic operations, said architecture comprising:

an array of substantially identical processing elements (PE) arranged in horizontal rows and vertical columns, each PE having electrically conductive lines running in the North, South, East and West directions connected to neighboring PEs in those directions, respectively;

the North and South lines being connected together to form a vertical line, with the East and West lines being connected together to form a horizontal line;

each PE having a node with a programmable voltage level thereon representing a given logical state of the PE, the array being arranged so that said logical state on the node can be simultaneously shared between PEs which are connected together;

a vertical gate connected between the vertical line and the node in each PE to thereby permit selective connection of PE nodes in a column together;

a horizontal gate connected between the horizontal line and the node in each PE to thereby permit selective connection of PE nodes in a row together;

control means for opening and closing the gates; and

memory means in each PE coupled to said node for storing a some/none result related to whether some or none of the nodes of the connected PEs are in a given logical state.

2. The architecture of claim 1 which further comprises a West gate in the West line, with the control means being adapted to open and close said West gate.

3. The architecture of claim 1 which further comprises:

an East gate in the East line, with the control means being adapted to open and close said East gate.

4. The architecture of claim 1 which further comprises:

a North gate in the North line, with the control means being adapted to open and close said North gate.

5. The architecture of claim 1 which further comprises:

a South gate in the South line, with the control means being adapted to open and close said South gate.

6. The architecture of claim 1 which further comprises:

a Northwest gate between the North line and the West line, with the control means being adapted to open and close said Northwest gate.

7. The architecture of claim 1 which further comprises:

a Northeast gate between the North line and the East line, with the control means being adapted to open and close said Northeast gate.

8. The architecture of claim 1 wherein each PE includes:

a programmable digital memory; and

a multi-bit control register coupled to the memory, each bit in the control register determining whether a particular gate is opened or closed.

9. The architecture of claim 1 wherein each processing element is a bit serial processor including an arithmetic logic unit.

10. An image understanding machine comprising:

a first level of image processing elements for operating on an image matrix on a pixel per processing element basis;

a second level of processing elements associated with a group of first level processing elements;

a third level of processing elements associated with a given number of second level processing elements;

a host computer communicating with at least the third level processing element; and

said first level of processing elements being an N×

N array of bit serial processors including an arithmetic logic unit and a multi-bit memory, each PE having electrically conductive lines running in the North, South, East and West directions connected to neighboring first level PEs in those directions, respectively;

the North and South lines being connected together to form a vertical line, with the East and West lines being connected together to form a horizontal line;

a node having a programmable voltage level thereon, a vertical gate connected between the vertical line and the node, a horizontal gate connected between the horizontal line and the node, a North gate in the North line, an East gate in the East line, a South gate in the South line, a West gate in the West line, a Northeast gate connected between the North line and the East line, a Northwest gate connected between the North line and the West line;

control means for controlling the opening and closing of said gates; and

a some/none line coupled between the node and the memory whereby the state of the some/none line is a function of the voltage level on the nodes of those PEs which are connected together by said gate.

11. The machine of claim 11 wherein each PE includes register means coupled to the node for controlling the voltage level thereon.

12. The machine of claim 12 wherein said control means comprises a multi-bit register, with the states of the bits of each register controlling the opening and closing of an associated gate.