Vertical transistor device fabricated with semiconductor regrowth

• US 4,903,089 A
• Filed: 02/02/1988
• Issued: 02/20/1990
• Est. Priority Date: 02/02/1988
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Hollis, Mark A., Bozler, Carl O., Nichols, Kirby B., Bergeron, Normand J. Jr.
• Primary Examiner(s): LARKINS, WILLIAM
• Application Number:
  US07/151,395
• Time in Patent Office: 749 Days
• Field of Search: 357/22 E, 357/22 C, 357/22 D, 357/22 I, 357/55, 357/15
• US Class Current: 257/256
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66454 Static induction transistors [SIT], e.g. permeable base transistors [PBT]
• CPC Class Codes: H01L 29/66856 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A vertical transistor device is characterized by active regions vertically separated by a narrower control region. The control region is defined by conducting layer extensions which extend into a groove within which semiconductor material is regrown during device fabrication. The device is further characterized by regions of isolating material, located horizontally adjacent to the active regions, said isolating material serving to reduce parasitic capacitance and improve thermal distribution within the device, thereby improving frequency and power performance.

Claims

1. A vertical transistor device comprising one or more active cells which comprise:

a. first and second semiconductor regions vertically displaced in semiconductor material and separated by a control region;

b. isolation regions adjacent to the sides of the first and second semiconductor regions, the isolation regions being formed of a material which is different from the semiconductor material and which has a lower dielectric constant; and

c. a conducting layer extending from at least one isolation region, thereby defining the control region, said control region being narrower than at least one of either the first or second semiconductor regions wherein the conducting layer extends beyond the isolation region material to a distance on the order of the zero bias depletion width of the semiconductor due to the isolation region material to semiconductor interface.

2. A vertical transistor device as in claim 1 wherein the conducting layer vertically separates the isolation layers adjacent the first and second semiconductor regions.

3. A vertical transistor device as in claim 1 wherein the conducting layer comprises a grating.

4. A Vertical transistor device as in claim 3 wherein the grating forms depletion regions which form current-limiting channels.

5. A vertical transistor device as in claim 3 which comprises a vertical field effect transistor.

6. A vertical transistor device as in claim 3 wherein the space between teeth of the grating defines the control region.

7. A vertical transistor device as in claim 6 wherein the width of the control region is less than the width of the first and second semiconductor regions.

8. A vertical transistor device as in claim 3 wherein the conducting layer is selected from the group consisting of tungsten and doped poly-silicon.

9. A vertical transistor device as in claim 3 wherein the isolation layers contain material selected from the group consisting of diamond, beryllium oxide, aluminum oxide, aluminum nitride, silicon dioxide, silicon nitride, air, and foamed polymeric materials.

10. A vertical transistor device as in claim 3 wherein the semiconductor material is gallium arsenide.