Data collecting method and apparatus for loop-linked control system

• US 4,903,190 A
• Filed: 01/29/1988
• Issued: 02/20/1990
• Est. Priority Date: 01/30/1987
• Status: Expired due to Term

• Current Assignee: Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Akai, Takumi
• Primary Examiner(s): RUGGIERO, JOSEPH F
• Application Number:
  US07/150,049
• Time in Patent Office: 753 Days
• Field of Search: 364/130-137, 364/551, 364/200, 364/900, 364/551.01, 371/10, 371/21, 371/22, 371/34, 371/68, 370/86, 370/88, 340/825.05, 340/825.06
• US Class Current: 700/2
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004

Abstract

A method of data transmission for a loop-linked processor system enabling an easy access to the internal memories of the processors which are normally not directly accessible from the data transmission loop. The method includes the steps of reserving one portion of each common memory for a command signal from one processor commanding to bring data in the internal memory of another processor to the common memory of the corresponding transmission controller: bringing data in the internal memory of one of the processors to the common memory of the corresponding transmission controller, only when the command signal from another processor is received; and reserving another portion of each common memory for those data originally in the internal memory of one processor which has been brought to the common memory of the corresponding transmission controller.

Claims

1. A method of data transmission for a loop-linked processor system in which a plurality of processor means are linked together by a data transmission loop through a plurality of transmission controller means, each processor means having an internal memory not directly accessible from the data transmission loop, each transmission controller means having a common memory directly accessible from the data transmission loop, the method comprising the steps of:

reserving a first portion of each common memory for a command signal from one processor means commanding to bring data in the internal memory of another processor means to the common memory of the corresponding transmission controller means;

bringing data in the internal memory of one of the processor means to the common memory of the corresponding transmission controller means, only when the command signal from another processor means is received; and

reserving a second portion of each common memory for those data originally in the internal memory of one processor means which has been brought to the common memory of the corresponding transmission controller means.

2. The method of claim 1, further comprising the step of registering those data originally in the internal memory of one processor means which has been brought to the common memory of the corresponding transmission controller means, into said second portion of each common memory reserved for such data.

3. The method of claim 1, further comprising the step of monitoring those data originally in the internal memory of monitoring those data originally in the internal memory of one processor means which has been brought to the common memory of the corresponding transmission controller means.

4. The method of claim 1, further comprising the step of controlling an entire loop-linked processor system by one of the processor means.

5. An apparatus of data transmission for a loop-linked processor system, comprising:

a plurality of transmission controller means mutually communicable through a data transmission loop, each transmission controller means having a common memory directly accessible from the data transmission loop;

a plurality of processor means each of which is linked to the data transmission loop through one of the transmission controller means, each processor means having an internal memory not directly accessible from the data transmission loop;

a first portion of each common memory being reserved for a command signal from one processor means commanding to bring data in the internal memory of another processor means to the common memory of the corresponding transmission controller means;

data in the internal memory of one of the processor means being brought to the common memory of the corresponding transmission controller means, only when the command signal from another processor means is received; and

a second portion of each common memory being reserved for those data originally in the internal memory of one processor means which has been brought to the common memory of the corresponding transmission controller means.

6. The apparatus of claim 5, wherein one of the processor means is a programmable controller for registering those data originally in the internal memory of one processor means which has been brought to the common memory of the corresponding transmission controller means, into said second portion of each common memory reserved for such data.

7. The apparatus of claim 5, wherein one of the processor means is a monitor means by which those data originally in the internal memory of one processor means which has been brought to the common memory of the corresponding transmission controller means can be monitored.

8. The apparatus of claim 5, wherein one of the processor means is a central processing unit for controlling an entire loop-linked processor system.