Numerical control system for highly dynamic processes

• US 4,903,213 A
• Filed: 11/30/1987
• Issued: 02/20/1990
• Est. Priority Date: 12/01/1986
• Status: Expired due to Term

• Current Assignee: AG FUR INDUSTRIELLE ELEKTRONIK AGIE LOSONE B. LOCARNO CH-6616 LOSONE, SWITZERLAND
• Original Assignee: A.G. Fur Industrielle Elektronik Agie
• Inventors: Buhler, Ernst, Boccadoro, Marco
• Primary Examiner(s): MACDONALD, ALLEN R
• Application Number:
  US07/126,267
• Time in Patent Office: 813 Days
• Field of Search: 364/474.31, 364/182, 364/702, 364/723, 364/853, 318/573
• US Class Current: 700/189
• CPC Class Codes: G05B 19/4103 Digital interpolation
• CPC Class Codes: G05B 2219/34047 Dsp digital signal processor
• CPC Class Codes: G05B 2219/34101 Data compression, look ahead segment calculation, max segment lenght
• CPC Class Codes: G05B 2219/34167 Coarse fine, macro microinterpolation, preprocessor
• CPC Class Codes: G05B 2219/45221 Edm, electrical discharge machining, electroerosion, ecm, chemical

Abstract

A numerical control system performs path interpolation calculations for the control of highly dynamic processes having different path contour geometries wherein a vector having a length L connects in linear form a first point P1 to a second point P2. These points are located in three dimensional Cartesian space having axes x, y, and z. Length L has Cartesian components X, Y and Z and is subject to an angular rotation C about the z axis. The system also has process parameters S and K wherein S is an address identifying the parameter to be modified and K identifies the modified parameter value. A coarse interpolator outputs the path elements L, X, Y, Z and C and the parameters S and K between path increments as course interpolations which are a function of the path contour geometry but are independent of time frame. A fine interpolator having an intermediate memory is connected downstream from the course interpolator. The fine interpolator outputs the path elements and parameters as fine interpolations. The intermediate memory receives, for intermediate storage and subsequent processing, the course interpolations from the course interpolator. There is no joint fixed grid frame for data exchange between the two interpolators. Control means operates in time independence from the coarse interpolator and controls the fine interpolator with its memory to perform the fine interpolation steps and the outputting of parameters S and K in real time.

Claims

1. A numerical control system for performing path interpolation calculations for the control of highly dynamic processes having different path contour geometries wherein a vector having a length L connects in linear form a first point P1 to a second point P2, said first and second points being located in three dimensional Cartesian space having axes x, y, and z, length L having Cartesian components X, Y and Z and being subject to an angular rotation C about the z axis, the system also having process parameters S and K wherein S is an address identifying the parameter to be modified and K identifies the modified parameter, said system comprising:

a coarse interpolator means for performing coarse interpolations of and outputting path elements L, X, Y, Z and C and the parameters S and K between path increments wherein said course interpolations are a function of the path contour geometry but are independent of a time grid;

a master fine interpolator means for performing fine interpolations of said path elements and parameters and including an intermediate memory and being connected downstream from the course interpolator means and receiving, intermediately storing, subsequently processing the coarse interpolations from said coarse interpolator means, and outputting said path elements and parameters as fine interpolations, wherein there is no joint fixed grid frame for data exchange between the coarse interpolator means and the fine interpolator means; and

control means operating in time independence from the coarse interpolator means for controlling the fine interpolator means so that said memory thereof performs fine interpolation steps and the outputting of parameters S and K in real time.

2. The system of claim 1 wherein the coarse interpolator means is a programmable computer.

3. The system of claim 2 wherein the coarse interpolator means is a personal computer programmable in a known language.

4. The system of claim 3 wherein the computer is constructed so that is does not use angle functions and employs floating point arithmetic.

5. The system of claim 4 wherein the computer has a digital single chip floating point signal processor.

6. The system of claim 1 wherein the coarse interpolator means includes means for calculating the path elements in such manner that only such vector lengths L are allowed which ensure that a maximum deviation of a vector length from the contour to be interpolated does not exceed a predetermined value.

7. The system of claim 6 wherein the coarse interpolator means is constructed so that when calculating the path elements (L, X, Y, Z, C) only those vector lengths (L) are allowed which in the fine interpolator means will not produce for any vector position a final error in the components (X, Y, Z, C) and wherein admissible vector lengths (L) are determined with the aid of a mathematical simulation or a test run of said fine interpolator means and are stored in a table form in said coarse interpolator means.

8. The system of claim 7 wherein the coarse interpolator means is constructed in such a way that when calculating the path elements (L, X, Y, Z, C) it takes account of rounding errors occuring during a quantization necessary for the fine interpolator means when calculating the path elements (L, X, Y, Z, C) and checks prior to each calculation of the path elements (L, X, Y, Z, C) whether a path end point can be reached with a permitted vector length (L) and in this case selects a final component (X, Y, Z, C) in such a way that a final error is reduced to zero.

9. The system of claim 8 wherein the coarse interpolator means is constructed so that it multiplies the calculated path elements (L, X, Y, Z, C) by a numerical factor (N) indicating how often the fine interpolator means successively interpolates a vector length (L).

10. The system of claim 1 wherein the fine interpolator means includes at least one programmable frequency divider which has a pulse rate multiplier with a counter, axial component registers (X/L, Y/L, Z/L, C/L) and an exclusive-OR circuit, in which

(a) the counter has:

(a.1) an input which is programmed to a starting value equal to a determined vector length (L),

(a.2) a clock input for a servo-path frame clock signal (T),

(a.3) a direction input for a servo-direction signal (R), and

(a.4) an output connected to said axial component registers, and

(b) each of the axial component registers (X/L, Y/L, Z/L, C/L) has an input for an additional direction information and an axial output (TX, TY, TZ, TC), and

(c) the exclusive OR circuit has a plurality of gates equal in number to the number of said registers, each gate being responsive at one input thereof to the servo-direction signal (R) and another input thereof to the associated axial component register (X/L, Y/L, Z/L, C/L) and consequently determines movement directions (RX, RY, RZ, RC, TC) of axial outputs (RX, TX, RY, RZ, TZ, RC, TC) of said frequency divider.

11. The system of claim 10, wherein said control means is a time independent control system which has a priority decoder and is designed in such a way that

(a) it only operates when

(a.1) said coarse interpolator means loads a data word into said intermediate memory, or

(a.2) said coarse interpolator means directly introduces a manual control into a process, or

(a.3) a servo-path frame clock signal (T) is to be processed, and

(b) in the case of a simultaneous application of several signals, said priority decoder determines a hierarchy of said signals.

12. The system of claim 11 wherein the fine interpolator means includes at least one fixed-programmable sequential logic component and at least one array logic component.

13. The system of claim 12, wherein the fine interpolator means is constructed from hard-wired logic, and further comprises a fixed programmed program memory coupled to said priority decoder, a status register coupled to said program memory, said intermediate memory being connected to said program memory, at least one programmable frequency divider connected to said program memory, a process parameter output circuit also connected to said program memory and a counter connected to said program memory and acting as a program counter, and an oscillator connected to the counter and being responsive to the priority decoder and having a starting input connected to said priority decoder and a stop input connected to said program counter.

14. The system of claim 13 wherein the fixed-programmed program memory is designed to activate one of several program sequences as a function of signals from the priority decoder and the status register.

15. The system of claim 14 wherein the fixed-programmed program memory is constructed so as to activate a program sequence when the servo-direction signal (R) on said counter indicates a negative direction, the data from said intermediate memory being read out and ordered in a reverse sequence and a backward fine interpolation being performed at the most back point to the starting point.

16. The system of claim 15, further including additional fine interpolators provided for a process, said additional fine interpolators being synchronized with one another by means of the servo path frame clock signal (T) and the servo-direction signal (R) on said counter.

17. The system of claim 15, and further including at least one slave fine interpolator, having a servo-path frame clock signal (T) and servo-direction signal (R) provided by a controllable oscillator, the controllable oscillator being controlled by means of the process parameters (S,K) of the master fine interpolator means.

18. The system of claim 17 wherein a switching matrix is provided which is connected downstream of the axial outputs (RX, TX, RY, TY, RZ, TZ, RC, TC) and by means of the process parameters (S, K) outputted by the fine interpolator means, said switching matrix connecting the axial outputs RX, TX, RY, TY, RZ, TZ, RC, TC) with different drive shafts (R₁, T₁, R₂, T₂, . . . R_n, T_n).

19. The system according to claim 11 wherein the fine interpolator means is substantially a programmable microcomputer which is designed in such a way that on a hierarchy basis:

(a) its algorithm, process parameters and geometrical data are loaded by the coarse interpolator means into said intermediate memory,

(b) it introduces via said coarse interpolator means manually inputted instructions directly into the process, and

(c) it performs a fine interpolation of servo path frame clock signals (T) and supplies said signals to the axial outputs (RX, TX, RY, TY, RZ, TZ, RC, TC).

20. The system of claim 19 wherein the intermediate memory includes a non-volatile memory medium and the intermediate memory is designed so as to store all information required by the system in order to be able to repeat a process at random.

21. The system of claim 20 wherein the non-volatile memory medium is connected between the coarse interpolator means and the fine interpolator means.

22. The system of claim 21 wherein a local data network (LAN is provided for the flow of data between the coarse interpolator means and the fine interpolator means.

23. The system of claim 22 wherein the fine interpolator means is constructed so as to feed back to the coarse interpolator means an information concerning a system state, process state and/or the geometrical points reached.

24. The system of claim 23 wherein the intermediate memory is designed to receive the process parameters (S, K) including geometry-dependent data indicative of acceleration or deceleration for a servosystem.