Method for wiring semiconductor integrated circuit device

• US 4,903,214 A
• Filed: 12/18/1987
• Issued: 02/20/1990
• Est. Priority Date: 12/26/1986
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hiwatashi, Tamotsu
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Cosimano, Edward R.
• Application Number:
  US07/135,085
• Time in Patent Office: 795 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/200, 364/300, 364/900 MS File
• US Class Current: 716/129
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Abstract

A method for wiring a semiconductor integrated circuit device includes a first step of assigning wiring routes for globally wiring cells of a plurality of cell rows to the cell arrays and the channel regions, in accordance with a wiring request for realizing a predetermined circuit operation, so as to obtain a plurality of nets, a second step of extracting X lines, extending along the channel regions, from the nets, a third step of combining the X lines in a plurality of line groups, in accordance wich X-coordinates of the X lines, and assigning the line groups to tracks of the channel regions, and a fourth step of determining a position of at least one cell row through which a Y line of the net passes, in order to connect the cells corresponding to the nets via the corresponding X lines.

Claims

1. A method for wiring a semiconductor integrated circuit device having a plurality of cell rows each containing a plurality of cells respectively having cell terminals, and channel regions arranged between adjacent cell rows, comprising:

a first step of assigning wiring routes for globally wiring cells of said plurality of cell rows to said cell rows and said channel regions, in accordance with a wiring request for realizing a predetermined circuit operation to obtain a plurality of nets with each net of said plurality of nets having at least a single X line and a single Y line;

a second step of extracting trunks, extending along said channel regions from said nets;

a third step of combining said trunks into a plurality of trunk groups, in accordance with X-coordinates of said trunks, and assigning the trunk groups to tracks of said channel regions; and

a fourth step of determining a position of at least one cell row through which the Y line of each net of said plurality if nets passes, in order to perform through wiring for the cells corresponding to each of said plurality of nets.

2. A method according to claim 1, wherein the third step includes a sub-step of dividing at least one of said nets into a plurality of trunks, in accordance with coordinates of the corresponding cell rows and terminals of the cell, and a sub-step of connecting at least one of said nets, using a branch perpendicular to said divided trunks.

3. A method according to claim 1, wherein the third step includes a sub-step of determining coordinates of virtual two edges, using said trunks as segments having a length greater, by a given margin, than an actual value, and a sub-step of assigning said trunks to the tracks, based on the coordinates of the virtual two edges.

4. A method according to claim 1, wherein the third step includes a sub-step of determining an assignable range of channel regions with respect to two edges of each of said nets, and a sub-step of selecting other nets each having at least a common portion of ranges of the channel regions to be assigned and having a trunk having a distal edge adjacent to a rear edge of the trunk of each of said nets, and combining these trunks in the trunk groups.

5. A method according to claim 1, wherein the second step includes a sub-step of dividing at least one of said trunks into a plurality of line segments and extracting the line segments, and the third step includes a sub-step of combining the divided line segments with other trunks.

6. A method according to claim 1, wherein the third step includes a sub-step of detecting coordinates of two edges of the extracted trunks, and a sub-step of arranging another trunk having a coordinate adjacent to the coordinate of at least one of the two edges of each of said trunks.

7. A method according to claim 6, wherein the third step includes a sub-step of connecting the cell terminals of said nets, which have a common channel determined by the cell row corresponding to the cell terminals constituting each of said nets, through a common track.

8. A method for wiring a semiconductor integrated circuit device having a plurality of cell rows which are formed on a semiconductor chip and are arranged along an X direction, and each of which is constituted by a plurality of cells having terminals, and channel regions arranged between the adjacent cell rows, comprising:

a first step of assigning wiring routes for globally wiring cells of said plurality of cell rows to said cell rows and said channel regions selectively having at least one track, in accordance with a wiring request for realizing a predetermined circuit operation to obtain a plurality of nets each having at least a single X line and a single Y line;

a second step of extracting a plurality of X lines, extending along said channel regions, from said nets;

a third step of combining said X lines in a plurality of line groups, in accordance with X-coordinates of said X lines, and assigning the line groups to tracks of said channel regions; and

a fourth step of determining a position of at least one cell row through which the Y line of each net of said plurality of nets passes, in order to perform through wiring for the cells corresponding to each of said plurality of nets.

9. A method according to claim 8, wherein the second step includes a sub-step of dividing at least one of the X-lines into a plurality of line components and extracting the line components, and the third step includes a sub-step of combining the line components with main lines of other nets.

10. A method according to claim 8, wherein the third step includes a sub-step of dividing at least one of said nets into a plurality of X lines, in accordance with coordinates of the corresponding cell rows and terminals of cells, and a sub-step of connecting the at least one of said nets using a line perpendicular to said divided X lines.

11. A method according to claim 8, wherein the third step includes a sub-step of determining coordinates of virtual two edges, using said X lines as lines having a length greater, by a given margin, than an actual value, and a sub-step of assigning said X lines to the tracks, based on the coordinates of the virtual two edges.

12. A method according to claim 8, wherein the third step includes a sub-step of detecting left- and right-edge coordinates of the extracted X lines, and a sub-step of arranging, in an identical tack, other X line having left-edges adjacent to the right-edges of said X line.

13. A method according to claim 12, wherein the third step includes a sub-step of connecting the terminals of cells of said nets, which have a common channel determined by the cell row corresponding to the terminals of cell constituting each of said nets, through a common track.