Method of identifying flag bits

• US 4,903,219 A
• Filed: 01/27/1988
• Issued: 02/20/1990
• Est. Priority Date: 01/27/1988
• Status: Expired due to Term

• Current Assignee: Snap-On Tools Company LLC (Snap-On Incorporated)
• Original Assignee: Sun Electronics Corp (Snap-On Incorporated)
• Inventors: Woodbury, Robert, Rzadzki, Robert J., Reynolds, Neal S.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US07/148,972
• Time in Patent Office: 755 Days
• Field of Search: 364/431.11, 364/431.05, 364/431.03, 364/551.01, 123/480, 123/456, 371/29, 371/20
• US Class Current: 714/805
• CPC Class Codes: G01M 15/05 by combined monitoring of two or more different engine parameters
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested

Abstract

A technique for determining and resetting one or more flags in a digital word in memory in which the flags comprise added bits in known locations different from any of the magnitude bits in the word. A sign bit is included and a flag is set by making its bit value differ from that of the sign bit. A digital word from the memory is AND'"'"'d with a bit mask to check the flag bit location. A parity routine is run to determine whether the flag bit is set, and if so, the memory location of the word and the type of flag is recorded. The word with the flag bit set is XOR'"'"'d with another bit mask to reset the flag bit so that the word may be returned to its memory location with the flag reset.

Claims

1. A method of identifying flag bits in signals gathered from an automotive engine and placed in a memory comprising a plurality of digital words having a fixed number of bits denoting magnitude one bit denoting sign and a flag bit in a known bit position, the flag being set when the bit value of the flag bit differs from that of the sign bit, comprising the steps of:

processing a digital word read out from a specific memory location to produce a digital result having the sign bit and the flag bit isolated;

conducting a parity test on the digital result to determine if the flag is set;

storing the memory address of a digital word in which the flag is set; and

repeating the steps for another digital word from the memory.

2. The method of claim 1 in which a second flag bit may be set and comprising the steps of:

repeating said processing step to isolate the sign bit and the second flag bit; and

conducting a parity test to determine whether the second flag is set.

3. A method of identifying flagged data in a memory in which data consists of digital words having a fixed number of bits representing magnitude and other bits in known bit positions including a sign bit representing the sign of the data and first and second flag bits corresponding to a cylinder #X firing event and a cylinder #1 firing event, respectively, a flag being set by having its bit value made opposite to that of the sign bit, comprising the steps of:

processing a digital word from the memory to isolate the sign bit and the first flag bit to produce a first digital result;

conducting a parity test on the first digital result to determine whether the first flag bit is set;

storing the memory address of the digital word if the first flag bit is set; and

if set

processing the digital word to isolate the sign bit and the second flag bit to produce a second digital result;

conducting a parity test on the second digital result to determine whether the second flag bit is set; and

storing the memory address of the digital word if the second flag bit is set.

4. A method of locating and processing flag bits in data in a memory characterized by a plurality of digital words having a fixed number of bits relating to magnitude, a sign bit and one or more flag bits in known bit positions, a flag being set by making its bit value opposite to that of the sign bit, comprising the steps of:

processing a digital word to isolate the sign bit and a first flag bit;

conducting a parity test to determine whether the first flag bit is set; and

if set

resetting the first flag in the digital word;

storing the memory address of the digital word and information indicating that the first bit is set; and

writing said digital word back to said memory with said first flag bit reset.

5. The method set forth in claim 4 in which a second flag bit may be set and comprising the steps of:

repeating said processing step to isolate the sign bit and the second flag bit, conducting a parity test to determine if the second flag is set; and

resetting said second flag bit;

storing the memory address of the digital word and information indicating that the second flag bit is set; and

writing the digital word back into memory with the first and the second flag bits reset.

6. A method of identifying flags in signals gathered from an automotive engine and placed in a RAM memory comprising a plurality of digital words, each signal having a magnitude defined by a fixed number of bits and flags defined by higher order bits than said fixed number of bits, and each said digital word including a sign bit, a flag being set when its bit value is opposite to that of the sign bit, comprising the steps of:

ANDing a digital word from the memory with a masking word in which all bits except the sign bit and a flag bit are masked to produce a first digital result;

conducting a parity test of the first digital result to determine whether the flag is set;

storing the RAM memory address of the digital word if the flag is set; and

repeating the process for another word from the memory.

7. The method of claim 6 wherein a second flag may be set, comprising the additional steps of:

ANDing the digital word with another masking word in which all bits except the sign bit and the second flag bit are masked to produce a second digital result; and

conducting a parity test of the second digital result to determine whether the second flag is set.

8. A method of identifying flagged data in a memory in which the data consists of digital words having a fixed number of bits representing magnitude and a group of more significant bits representing the sign of the data and first and second flag bits corresponding to a cylinder #X firing event and a cylinder #1 firing event, respectively, a flag being set by having its bit value made opposite to that of the sign bit, comprising the steps of:

ANDing a digital word from the memory with a masking word in which all bits except the first flag bit and the sign bit are masked;

conducting a parity test on the result to determine whether the first flag bit is set;

storing the memory address of the digital word if the first flag bit is set; and

if the first flag bit is set

ANDing with another masking word to mask all bits except the sign bit and the second flag bit;

conducting a parity test on the result to determine whether the second flag bit is set;

storing the memory address of the digital word if the second flag bit is set.

9. A method of locating flag bits in a memory characterized by a plurality of digital words having a fixed number of bits relating to magnitude, a sign bit and one or more higher order flag bits, a flag being set by making its bit value opposite to that of the sign bit, comprising the steps of:

ANDing a digital word with a masking word for masking all bits except the sign bit and the first flag bit;

conducting a parity test on the result to determine whether the first flag bit is set;

XORing the digital word with a masking word to reset the first flag bit;

storing the memory address of the digital word and information indicating that the first flag bit is set; and

writing said digital word back to said memory with said first flag bit reset.

10. The method set forth in claim 9 in which a second flag bit may be set and comprising the additional steps of:

repeating said steps of ANDing and XORing with appropriate masks for determining and resetting said second flag bit;

storing the memory address of the digital word and information indicating that the second flag bit is set; and

writing the digital word back into memory with the first and the second flag bits reset.