ID protected memory with a maskable ID template
First Claim
1. Access circuitry associated with a peripheral device for selectively gaining access thereto from the common data link, comprising:
- interface means for interfacing with the common data link for receiving ID information and control information from a common data link and transferring data between the common data link and the peripheral unit;
protocol means for receiving and storing control information and ID information received from the common data link;
ID storage means for storing a digital ID template corresponding to the ID information;
data transfer means for transferring data between said interface means and the peripheral device;
masking means for masking off a portion of said ID template in response to receiving a predetermined mask command in the control information, said predetermined mask command determining the portion of said ID template that is masked off;
compare means for comparing the unmasked portion of said ID template with the corresponding portion of the received ID information stored in said protocol means and outputting a match signal if a match is present between the unmasked portion of said ID template and the corresponding portion of the received ID information stored in said protocol means;
control means for controlling said data transfer means to transfer data to the peripheral device from said interface means in response to device Write control information stored in said protocol means, or from the peripheral device to said interface means in response to device Read control information stored in said protocol means;
inhibit means for inhibiting access to the peripheral unit by said data transfer means if a match signal is not generated by said compare means.
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Accused Products
Abstract
A remotely disposed RAM (12) is provided which is accessible by a centralized serial CPU (28) through a common data link. The RAM (12l ) is interfaced with the common data link through a serial port (19) and access thereto is controlled by an arbiter (10). The arbiter (10) includes a protocol shift register (31) for receiving control information, ID information and address information for the RAM (12). The ID information is compared with prestored identification information in an ID template (37). This ID template is operable to have a portion thereof masked off in response to receiving a mask command as part of the control information. If a match is present between the unmasked portion of the ID template and the corresponding portion of the ID information, access is allowed to the arbiter (10) and the RAM (12). A response is then transmitted to the common data link in the form of data read from the RAM.
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Citations
17 Claims
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1. Access circuitry associated with a peripheral device for selectively gaining access thereto from the common data link, comprising:
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interface means for interfacing with the common data link for receiving ID information and control information from a common data link and transferring data between the common data link and the peripheral unit; protocol means for receiving and storing control information and ID information received from the common data link; ID storage means for storing a digital ID template corresponding to the ID information; data transfer means for transferring data between said interface means and the peripheral device; masking means for masking off a portion of said ID template in response to receiving a predetermined mask command in the control information, said predetermined mask command determining the portion of said ID template that is masked off; compare means for comparing the unmasked portion of said ID template with the corresponding portion of the received ID information stored in said protocol means and outputting a match signal if a match is present between the unmasked portion of said ID template and the corresponding portion of the received ID information stored in said protocol means; control means for controlling said data transfer means to transfer data to the peripheral device from said interface means in response to device Write control information stored in said protocol means, or from the peripheral device to said interface means in response to device Read control information stored in said protocol means; inhibit means for inhibiting access to the peripheral unit by said data transfer means if a match signal is not generated by said compare means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An ID protected access circuit for interfacing with a common data link, comprising:
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receive circuitry for receiving ID information and a mask command from the common data link; ID storage means for storing as an ID template a digital word of a predetermined bit length; mask means for masking off a portion of said ID template in accordance with information in said mask command; compare means for comparing the unmasked portion of said ID template with the corresponding portion of the received ID information and outputting a match signal if a match is present between the unmasked portion of said ID template and the corresponding portion of the received ID information; and means for outputting a response to the common data link in response to generation of said match signal. - View Dependent Claims (10, 11, 12, 13)
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14. A method for accessing an ID protected access circuit that interfaces with a common data link, comprising:
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receiving ID information from the common data link; receiving a mask command from the common data link; prestoring as an ID template a digital word of a predetermined bit length; masking off a portion of the ID template in accordance with information in the mask command; comparing the unmasked portion of the ID template with the corresponding portion of the ID information and outputting a match signal if a match is present between the unmasked portion of the ID template and the corresponding portion of the received ID information; and outputting a response to the common data link in response to generation of the match signal. - View Dependent Claims (15, 16, 17)
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Specification