Method of manufacturing a DMOS device

• US 4,904,613 A
• Filed: 12/21/1987
• Issued: 02/27/1990
• Est. Priority Date: 12/23/1986
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Tree, Richard J., Whight, Kenneth, Coe, David J.
• Primary Examiner(s): Heaern, Brian E.
• Assistant Examiner(s): THOMAS, TOM
• Application Number:
  US07/135,880
• Time in Patent Office: 799 Days
• Field of Search: 357/23.4, 357/23.8, 437/27, 437/28, 437/29, 437/34, 437/40, 437/58, 437/186, 437/191, 437/200, 437/228, 437/233, 156/643
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method of manufacturing a semiconductor device in which a conductive layer (6) provided on a surface (4) of a semiconductor body (1) is formed with at least one opening (10). The semiconductor device may be an insulated gate field effect transistor (IGFET) in which case the opening (10) defines a hollow gate structure for the IGFET. Insulating material (16'"'"') is grown on the surface (4) to cover the conductive layer. The opening or openings (10) are sufficiently small and the growth of insulating material is continued for a sufficiently long period that insulating material growing on edges (8"a) of the conductive layer bounding the openings (10) meets to close the openings so that subsequent etching of the insulating material anisotropically towards the surface (4) to expose a surface of the conductive layer and/or to form a window (18) within insulating material covering an area of the semiconductor body surface larger than the openings and not covered by the conductive layer, leaves insulating material (19,17) on edges of the conductive layer so that the openings remain closed. Where the semiconductor device is an IGFET impurities to form the source and channel regions may be introduced via the window.

Claims

1. A method of manufacturing gas field effect transistor comprising the steps of:

(a) forming an insulating layer on a surface of a semiconductor body,

(b) forming at least one insulated gate structure on said insulating layer by providing separated conductive gate regions on said insulating layer,

(c) forming an opening through each of said conductive gate regions to said insulating layer, said opening being smaller than separation of said separated conductive gate regions,

(d) growing insulating material on said separated conductive gate regions for a period sufficient to close said opening through each of said conductive gate regions, said insulating material also being grown on said insulating layer between said separated conductive gate regions,

(e) anisotropically etching said insulating material toward said surface of said semiconductor body until said surface is exposed between said separated conductive gate regions, but insulating material remains on edges of said conductive gate regions and said openings remain closed, said insulating material remaining on said edges forming at least in part at least one window through said insulating material to said surface.

(f) introducing impurities through said at least one window to form source regions registered with said insulated gate regions, said source regions being of one conductivity type, and to form channel regions of an opposite conductivity type beneath said insulated gate regions.

2. A method according to claim 1, wherein said source regions are formed in regions of said semiconductor body of said opposite conductivity type, and wherein a portion of said body provides said channel regions, further comprising the steps of shorting a region of said semiconductor body to said source regions by

(g) providing at least one masking region extending across said at least one window to expose at least one area of said source regions,

(h) etching away the exposed areas of said source regions to expose portions of said semiconductor body,

(i) removing said at least one masking region, and

(j) providing metallization in said at least one window to short exposed portions of said semiconductor body to said source regions.

3. A method according to claim 2, wherein said at least one window is elongated, and wherein said at least one masking region extends completely across a width dimensions of said at least one window but only partly across a length dimension of said at least one window.

4. A method according to claim 3, wherein said conductive gate regions are formed elongated, wherein said opening extends in the length direction of said conductive gate region to form two conductive gate regions strips, wherein said at least one window is formed along said elongated length of said conductive gate regions, and wherein said step of introducing impurities forms respective source regions aligned with each elongated edge of said gate regions, said channel regions being formed respectively underlying each conductive gate region strip.

5. A method according to claim 1, wherein said step of anisotropically etching exposes upper surfaces of said conductive gate regions.

6. A method according to claim 1, further comprising the step of depositing metal on surfaces exposed by said step of anisotropically etching, wherein said metal reduces resistivity of said exposed surfaces.

7. A method according to claim 1, wherein said at least one of said surface of said semiconductor body and said conductive gate regions are formed of silicon, and wherein refractory metal silicides are formed on surfaces exposed by said step of anisotropically etching.

8. A method according to claim 1, wherein said conductive gate regions are formed elongated, wherein said opening extends in the length direction of said conductive gate region to form two conductive gate region strips, wherein said at least one window is formed along said elongated length of said conductive gate regions, and wherein said step of introducing impurities forms respective source regions aligned with each elongated edge of said gate regions, said channel regions being formed respectively underlying each conductive gate region strip.