Method of manufacturing lateral IGFETS including reduced surface field regions

• US 4,904,614 A
• Filed: 05/23/1988
• Issued: 02/27/1990
• Est. Priority Date: 06/08/1987
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Fisher, Carole A., Coe, David J., Paxman, David H.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Quach, T. N.
• Application Number:
  US07/197,539
• Time in Patent Office: 645 Days
• Field of Search: 437/40, 437/41, 437/44, 437/45, 437/59, 437/61, 437/63, 437/64, 437/240, 437/247, 437/917, 437/934, 437/952, 437/968, 437/29, 437/28, 148/DIG. 96, 357/23.8, 357/52, 357/53
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of manufacturing a semiconductor device such as a lateral insulated gate field effect transistor is described in which impurities for forming first and second relatively shallow RESURF regions (8 and 11) of the opposite and the one conductivity type, respectively, are then introduced into the first region (4) and the semiconductor body is then heated first in an oxidizing atmosphere to cause the impurities to diffuse to form the RESURF regions (8 and 11) and to grow a relatively thick layer of insulating material on the given surface (3) at the same time. The relatively thick layer of insulating material is then defined to provide field oxide (14a) and gate oxide (14) then grown onto which is deposited a conductive gate layer (15,16) to form an insulated gate structure. Impurities are then introduced into the semiconductor body (3) using the insulated gate structure as a mask so as to form a lateral insulated gate field effect transistor (1).

Claims

1. A method of manufacturing a semiconductor device comprising a lateral insulated gate field effect transistor, which method comprises providing a semiconductor body having adjacent a given surface a first region of one conductivity type, first introducing impurities of the opposite conductivity type and then introducing impurities of the one conductivity type into the semiconductor body, heating the semiconductor body in an oxidising atmosphere to cause the introduced impurities to diffuse to define a first RESURF region of the opposite conductivity type adjacent the given surface and a second RESURF region of the one conductivity type within the first RESURF region adjacent the given surface and to grow a relatively thick layer of insulating material on the given surface overlying the first RESURF region, defining an insulated gate structure by providing a relatively thin region of insulating material on a first area of the given surface overlying the first RESURF region and providing a conductive layer extending on the relatively thin insulating layer and onto the relatively thick insulating layer and introducing impurities into the semiconductor body using the insulated gate structure as a mask to form source and drain regions aligned to the insulated gate structure with the second RESURF region providing a drain extension region aligning the drain region and the first RESURF region forming at least part of a well of the opposite conductivity type within which the source and drain regions are formed.

2. A method according to claim 1, wherein the step of defining the insulated gate structure includes opening a window in the relatively thick insulating layer overlying the second RESURF region to enable introduction of the impurities to form the drain region and wherein, prior to opening the window, impurities of the opposite conductivity type are introduced using the insulated gate structure as a mask to form a subsidiary region of the well aligned to the insulated gate structure and adjoining the first RESURF region so that, after introduction of the impurities to form the source and drain regions, the source region lies within the subsidiary region and defines therewith a conduction channel area underlying the insulated gate structure to provide a connection between the source and drain regions.

3. A method according to claim 2, wherein the step of defining a window through the relatively thick insulating layer covering the drain extension region comprises defining a window in the conductive material on the relatively thick insulating material layer, etching the relatively thick insulating material using the window in the conductive layer as a mask using an isotropic process to define a window in the relatively thick insulating layer and then selectively etching the conductive layer with at least part of the upper surface of the conductive layer surrounding the window masked to remove conductive material overhanging the edge of the window formed in the relatively thick insulating material layer.

4. A method according to claim 3, which comprises wet etching the relatively thick insulating material to define the window in the relatively thick insulating material layer and then plasma etching the conductive material to remove the conductive material overhanging the edge of the window in the relatively thick insulating material layer.

5. A method according to claims 1, 2, 3, or 4 which comprises providing a vertical insulated gate field effect transistor at the same time as the lateral IGFET by introducing impurities into a further area of the given surface to provide a body region of the opposite conductivity type adjacent the given surface and a further source region of the one conductivity type within the body region and to provide a further insulated gate overlying a channel area of the body region to provide a connection between the further source region and the first region which forms the drain region of the vertical IGFET.

6. A method according to claim 5, which comprises introducing into the first region impurities for forming a relatively highly doped relatively deep region of the opposite conductivity type for the vertical IGFET and causing partial diffusion of the introduced impurities into the semiconductor body prior to introducing the impurities for forming the first and second RESURF regions so that the heating in the oxidising atmosphere also defines, for the vertical IGFET, the relatively deep relatively highly doped region which after formation of the source and drain regions extends through but is laterally surrounded by the body region of the vertical IGFET.

7. A method according to claims 1, 2, 3, or 4 which comprises introducing into the first region impurities for forming a relatively highly doped relatively deep region of the opposite conductivity type for the lateral IGFET and causing partial diffusion of the introduced impurities into the semiconductor body prior to introducing the impurities for forming the first and second RESURF regions so that the heating in the oxidising atmosphere also defines, for the lateral IGFET, the relatively deep relatively highly doped region which after formation of the source and drain regions extends through but is laterally surrounded by the subsidiary region of the well of the lateral IGFET.

8. A method according to claims 1, 2, 3, or 4 which comprises carrying out the step of heating the semiconductor body by heating the body first in a dry oxygen atmosphere and then in a wet oxygen atmosphere.