Differential amplifier incorporating negative resistance

• US 4,904,952 A
• Filed: 10/06/1988
• Issued: 02/27/1990
• Est. Priority Date: 10/12/1987
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanimoto, Hiroshi
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US07/254,242
• Time in Patent Office: 509 Days
• Field of Search: 330/252, 330/253, 330/258, 330/259, 330/261, 330/300, 333/213, 333/217
• US Class Current: 330/252
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 3/45103 Non-folded cascode stages

Abstract

A differential amplifier capable of achieving a large amplification, a wide frequency range, a high common mode rejection ratio, and a wide dynamic range simultaneously includes a device to produce negative resistance connected to output terminals. The differential amplifier also includes level shift circuits to generate additional voltages.

Claims

1. A differential amplifier, comprising:

first input terminals;

first output terminals;

first load resistor means connected to the first output terminals for generating output voltages;

first negative resistance means for producing negative such that a resistance value in a numerator of a fraction expressing the gain of the differential amplifier is maximized, the first negative resistance means including first level shaft circuit means for producing additional voltages, the first negative resistance means being connected to the first output terminals;

a first pair of transistors having emitters connected to each other, collectors connected to the first output terminals, and bases coupled to the first input terminals; and

first current source means connected to the emitters of the first pair of transistors for providing emitter currents to the first pair of transistors.

2. The amplifier of claim 1, wherein the first negative resistance means includes:

a second pair of transistors having emitters connected to each other and collectors connected to the base of the other transistor of the second pair of transistors as well as to the first output terminals; and

second current source means connected to the emitters of the second pair transistors for providing emitter currents to the second pair of transistors;

a terminal resistor connected between emitters of the second pair of transistors; and

wherein

the first level shift circuit means is connected between the base of each transistor of the second pair of transistors and the first output terminals.

3. The amplifier of claim 1, wherein the first level shift circuit means comprises a battery.

4. The amplifier of claim 1, wherein the first level shift circuit means comprises at least one diode.

5. The amplifier of claim 1, wherein the first level shift circuit means comprises at least one transistor with its base connected to its own collector.

6. The amplifier of claim 1, wherein the first level shift circuit means comprises a transistor with its base-emitter voltage amplified.

7. The amplifier of claim 1, wherein the first level shift circuit means comprises a resistor.

8. The amplifier of claim 2, further comprising first capacitor means connected to the first output terminals for accumulating charges, and wherein the first current source means is a variable current source.

9. The amplifier of claim 2, wherein the second current source means is a variable current source, and wherein the resistance of the terminal resistor is small.

10. The amplifier of claim 8, further comprising:

a second differential amplifier, comprising;

second input terminals;

second output terminals;

second load resistor means connected to the second output terminals for generating output voltages;

second negative resistance means for producing negative resistance connected to the second output terminals and including;

a third pair of transistors having emitters connected to each other, collectors connected to the base of the other transistor of the third pair of transistors as well as to the second output terminals;

second variable current source means connected to the emitters of the third pair of transistors for providing emitter currents to the third pair of transistors;

second level shift means, connected between the base of each transistor of the third pair of transistors and the second output terminals, for producing additional voltages; and

second capacitor means connected to the second output terminals for accumulating charges;

a fourth pair of transistors having emitters connected to each other, collectors connected to the second output terminals, and bases coupled to the second input terminals;

constant current source means connected to the emitters of the fourth pair of transistors for providing emitter currents to the fourth pair of transistors, wherein the first output terminals are connected to the second input terminals, and the first input terminals are connected to the second output terminals in a direction reverse to the connection between the first output terminals and the second input terminals;

third output terminals connected to the first input terminals; and

third input terminals connected to the first output terminals;

wherein the transistors are Metal Semiconductor Field Effect Transistors.

11. The amplifier of claim 1, wherein the transistors are heterojunction bipolar transistors.

12. The amplifier of claim 1, wherein the transistors are MESFETs.

13. The amplifier of claim 1, wherein the transistors are Metal Oxide Semiconductor Field Effect Transistors.

14. The amplifier of claim 1, wherein the transistors are Junction Field Effect Transistors.

15. The amplifier of claim 2, wherein the transistors of the second pair of transistors are heterojunction bipolar transistors.

16. The amplifier of claim 1, wherein the transistors of the second pair of transistors are Metal Semiconductor Field Effect Transistors.

17. The amplifier of claim 2, wherein the transistors of the second pair of transistors are Metal Oxide Semiconductor Field Effect Transistors.

18. The amplifier of claim 2, wherein the transistors of the second pair of transistors are Junction Field Effect Transistors.

19. The amplifier of claim 1, further comprising an emitter degeneration resistor between the emitters of the first pair of transistors.

20. The amplifier of claim 2, wherein the first level shift circuit means comprises a battery.

21. The amplifier of claim 2, wherein the first level shift circuit means comprises at least one diode.

22. The amplifier of claim 2, wherein the first level shift circuit means comprises at least one transistor with its base connected to its own collector.

23. The amplifier of claim 2, wherein the first level shift circuit means comprises a transistor with its base-emitter voltage amplified.

24. The amplifier of claim 2, wherein the first level shift circuit means comprises a resistor.

25. The amplifier of claim 2, further comprising an emitter degeneration resistor between emitters of the first pair of transistors.

26. A differential amplifier, comprising:

first input terminals;

first output terminals;

first load resistor means connected to the first output terminals for generating output voltages;

first negative resistance means for producing negative resistance such that a resistance value in a numerator of a fraction expressing the gain of the differential amplifier is maximized, the first negative resistance means including first level shift circuit means for producing additional voltages, the first negative resistance means being connected to the first output terminals;

a first pair of transistors having source terminals connected to each other, drain terminals connected to the first output terminals, and gate terminals coupled to the first input terminals; and

first current source means connected to the source terminals of the first pair of transistors for providing currents to the first pair of transistors.

27. The amplifier of claim 26, wherein the first negative resistance means includes:

a second pair of transistors having source terminals connected to each other and drain terminals connected to the gate terminal of the other transistor of the second pair of transistors as well as to the first output terminals; and

second current source means connected to the source terminals of the second pair of transistors for providing currents to the second pair of transistors;

a terminal resistor connected between source terminals of the second pair of transistors; and

wherein

the first level shift circuit means is connected between the gate terminal of each transistor of the second pair of transistors and the first output terminals.