Analog/digital data storage system

• US 4,905,003 A
• Filed: 07/24/1987
• Issued: 02/27/1990
• Est. Priority Date: 07/24/1987
• Status: Expired

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Martin A. Schwartz, Richard J. Helferich
• Inventors: Helferich, Richard J.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Young, Brian
• Application Number:
  US07/077,496
• Time in Patent Office: 949 Days
• Field of Search: 340/347 SH, 340/347 R, 340/347 M, 340/347 AD, 340/347 DA, 364/178, 364/179, 307/353, 381/31, 358/138, 455/38, 455/49, 455/53, 455/54, 455/68, 455/70, 455/72, 341/110, 341/122, 341/144, 341/155, 341/157, 341/200
• US Class Current: 341/110
• CPC Class Codes: G08B 3/1016 using wireless transmission calling systems using transmission by inductive loop H04B5/00
• CPC Class Codes: H04B 1/662 using a time/frequency relationship, e.g. time compression or expansion
• CPC Class Codes: H04M 1/725 Cordless telephones user interfaces specially adapted therefor H04M1/724

Abstract

An analog to digital data storage system includes receiver means for receiving an incoming signal carrying an analog component from a suitable transmitter. The analog signal is preferably preceded by a designated address code which is specific to a particular data storage system. The system further includes enable means activated by the incoming signal to emit an enable signal (logic high) to activate the system circuitry. The enable means may comprise a decoder which has been programmed to recognize an address code specified to a particular receiver or group of receivers or may be activated simply by the incoming signal without an address code, to emit the enable signal. The system also includes conversion means for converting the incoming analog data to digital format and memory means for storing the converted digital data. The conversion means further includes circuitry for reconverting a digital signal to analog format. Control means are provided for activating the conversion means and the digital memory storage means responsive to the enable signal from the decoder means. In the preferred embodiment, the control means also acts to deactivate the conversion means and memory means at the completion of the message or after a predetermined period of time. Switching means are included for activating the conversion means and the memory means for playback in analog format of any stored messages. the system further includes amplifier means for listening to incoming analog signals and playback of stored messages.

Claims

1. A digital voice storage communication system including:

at least one transmitting station selectively addressing and transmitting a communication packet including an address code followed by a voice message;

at least two receiving stations having a corresponding predetermined stored address, each comprising;

a. a receiver circuit for receiving an incoming signal carrying said communication packet;

b. decoder circuitry responsive to said receiver circuit for emitting a record enable signal responsive to said communication packet carried by said incoming signal, including;

a comparator for comparing said predetermined stored address with said communication packet address code and automatically generating said record enable signal in response to said comparison, without reference to a separate record enable signal from said transmitter;

c. digital memory for storing said voice message of said communication packet in response to said record enable signal;

d. signal conversion circuitry for converting digital data in said digital memory into analog data for playback.

2. The digital voice storage communication system of claim 1, wherein said decoder circuitry further includes circuitry for deactivating said digital memory when said record enable signal ceases.

3. The digital voice storage communication system of claim 1, additionally comprising an edge detector responsive to said receiver circuits and sensitive to an edge of said record enable signal for automatically resetting and initiating said digital voice storage communication system to permit said digital memory to record a new voice message.

4. The digital voice storage communication system of claim 1, additionally comprising a memory address selector for storing information indicative of available memory space to protect said memory from recording over previously stored messages.

5. The digital voice storage communication system of claim 2, wherein said decoder circuitry terminates said enable signal upon sensing the completion of a message.

6. The digital voice storage communication system of claim 2, additionally comprising a timer, wherein said decoder is responsive to said timer to terminate said enable signal upon expiration of a preset period of time thereby enabling said digital memory to record a new voice message.

7. The digital voice storage communication system of claim 1, wherein said decoder circuitry generates said record enable signal continuously for the duration of said incoming voice message.

8. The digital voice storage communication system of claim 1, wherein said decoder circuitry is voice actuated to generate said record enable signal responsive to said incoming voice message.

9. The digital voice storage communication system of claim 1, further including a timing circuit for clocking said voice message into said digital memory at a first data rate and for clocking data representing a stored voice message from said digital memory at a second data rated which is different from said first data rate.

10. The digital voice storage communication system of claim 1, wherein said transmitting station further comprises:

a second memory for storing voice messages at a third rate; and

a transmitting circuit for accessing voice messages from said second memory and transmitting said voice messages at a fourth rate, said fourth rate being higher than said third rate.

11. The digital voice storage communication system of claim 10, wherein said transmitting station further comprises an encoder generating said address code transmitted with said analog voice message in said communication packet.

12. A digital voice storage communication system as defined in claim 1, wherein said signal conversion circuitry converts said voice message of said communication packet from analog to digital format.

13. A digital voice storage communication system as defined in claim 1, wherein said communication packet additionally comprises command data and wherein said address code and said command data are followed with substantially no delay by said voice message in said communication data packet.

14. A digital voice storage communication system as defined in claim 1, wherein said communication packet includes a voice message whose length is variable.

15. A digital voice storage communication system as defined in claim 14, wherein said digital memory sequentially stores digital voice messages having different lengths.

16. A digital voice storage communication system as defined in claim 1, wherein said signal conversion circuitry operates during said record enable signal.

17. A digital voice storage communication system as defined in claim 1, additionally comprising:

an operator activated playback switch for retrieving said voice message stored in said digital memory and for activating said signal conversion circuitry.

18. A digital voice storage communication system as defined in claim 17, additionally comprising:

a switch for selection of said voice messages from said digital memory for conversion by said signal conversion circuitry.

19. A digital voice storage communication system as defined in claim 4, wherein said memory address selector generates a signal to erase the recorded voice message which has resided in said digital memory longer than any other stored message.

20. A digital voice storage communication system as defined in claim 1, wherein said digital memory records said voice messages silently.

21. A digital voice storage communication system including:

at least one transmitting station selectively addressing and transmitting a communication packet including an address code followed by a voice message;

at least two receiving stations each having a corresponding predetermined stored address, each comprising;

a receiving circuit responsive to said communication packet;

a decoder connected to said receiving circuit and generating a record enable signal in response to said communication packet;

a digital memory for storing said voice message of said communication packet in response to said record enable signal at a first data rate;

a signal conversion circuit for converting digital data into analog data, and

a timing circuit for clocking data representing said stored voice message from said digital memory at a second data rate which is different from said first data rate.

22. A digital voice storage communication system as defined in claim 21, wherein said decoder additionally comprises:

a comparator for comparing said predetermined stored address with said communication packet address code and automatically generating said record enable signal in response to said comparison, without reference to a separate record enable signal from said transmitter.

23. A digital voice storage communication system as defined in claim 21, wherein said conversion circuit converts said voice message of said communication packet from analog to digital format recording in said digital memory at said first data rate.

24. A digital voice storage communication system as defined in claim 21, wherein said signal conversion circuit terminates conversion of said voice message in said communication packet from analog data to digital data when said decoder ceases to generate said record enable signal.

25. A digital voice storage communication system as defined in claims 21, additionally comprising:

an edge detector circuit for automatic resetting of the digital voice storage communication system to permit said digital memory to record a new voice message.

26. A digital voice storage communication system as defined in claim 21, additionally comprising:

a timer for terminating said signal conversion circuit upon expiration of a predetermined period of time thereby enabling said digital memory to record a new voice message.

27. A digital voice storage communication system as defined in claim 21, wherein said communication packet has a voice message whose length is variable.

28. A digital voice storage communication system as stored in claim 21, wherein said digital memory sequentially stores digital voice messages having different lengths.

29. A digital voice storage communication system as defined in claim 21, additionally comprising:

an operator activated playback switch for retrieving said voice message stored in said digital memory and for initiating clocking of analog data representing said stored voice message at said second data rate.

30. A digital voice storage communication system defined in claim 21, additionally comprising:

a message indicator for alerting an operator of said voice message being received and recorded in said digital memory.

31. A digital voice storage communication system as defined in claim 21, wherein said communication packet additionally includes command data wherein said address code and said command data is followed with substantially no delay by said voice messages in said communication data packet.

32. A digital voice storage communication system as defined in claim 21, additionally comprising:

a record switch for allowing an operator to dictate messages for storing in said digital memory at said second rate.

33. A digital voice storage communication system as defined in claim 21, wherein said transmitting station additionally comprises:

a second memory for storing voice messages at a third rate, and

a transmitting circuit for accessing voice messages from said second memory and transmitting said voice messages at a fourth rate, said fourth rate being higher than said third rate.

34. A digital voice storage communication system as defined in claim 33, wherein said fourth rate is equal to said first rate.

35. A digital voice storage communication system as defined in claim 33, wherein said second memory stores messages in a stacked, sequential order.

36. A digital voice storage communication system as defined in claim 21, additionally comprising:

counter circuitry for monitoring said voice messages being recorded in said digital memory, said digital memory when full, simultaneously initializing said counter circuitry and enabling said digital memory to erase an oldest recorded voice message first.

37. A digital voice storage communication system as defined in claim 21, additionally comprising:

a message indicator for alerting an operator of said voice messages previously stored in said digital memory.

38. A digital voice storage communication system as defined in claim 21, wherein said communication packet additionally comprises:

rate data defining said first data rate.

39. A receiving station for receiving a communication packet including an address code followed by a compressed voice message, comprising:

a register storing a predetermined address for said receiving station;

a receiving circuit responsive to said communication packet;

a decoder connected to said receiving circuit for comparing said predetermined stored address with said communication packet address code and generating a record enable signal in response to said comparison;

a digital memory for storing said compressed voice message of said communication packet in response to said record enable signal at a first data rate;

a signal conversion circuit for converting digital data into analog data, and

a timing circuit for clocking data representing said stored compressed voice message from said digital memory at a second data rate which is slower than said first data rate to restore said voice message to its original frequency.

40. A receiver for receiving voice messages from a transmitter, the voice messages having been compressed at said transmitter thereby shifting their frequency upward, comprising:

a receiving circuit for receiving said compressed voice messages;

a digital memory connected to said receiving circuit, said digital memory storing digital data representing said compressed voice messages; and

a frequency shifting circuit connected to said memory for reproducing said stored voice messages in analog format at a rate which shifts the frequency of said stored voice messages to normal speech frequency.

41. A method of receiving a communication packet including an address code followed by a compressed voice message, comprising the steps of:

comparing said address code in said communication packet with a stored address and generating a record enable signal; and

recording digital data representing said voice message in a digital memory in response to said record enable signal alone.