Darlington transistor arrangement

• US 4,905,069 A
• Filed: 11/13/1984
• Issued: 02/27/1990
• Est. Priority Date: 11/10/1983
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Shigekane, Hisao
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US06/670,828
• Time in Patent Office: 1,932 Days
• Field of Search: 357/72, 357/46, 357/68, 357/76, 357/77, 357/75, 357/74, 357/81
• US Class Current: 257/567
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In the particular embodiment described in the specification, a Darlington transistor arrangement has a stepped upper surface with an emitter terminal of the preceding transistor disposed at the bottom of a groove formed between spaced raised portions on which the collector terminal and the emitter terminal of the transistor are located. A base terminal is disposed at a lower surface formed on the outside of the raised portion where either the collector terminal or the emitter terminal is situated, thereby providing sufficient insulation distance between terminals and avoiding the problem resulting from a crossing between the power wiring to the load or power source and the base driving wiring.

Claims

1. A Darlington transistor including a resin housing body having a stepped surface comprising alternating upper and lower planar portions;

a collector terminal and an emitter terminal formed on respective upper portions of the stepped surface;

a base terminal and an emitter-base terminal formed on respective lower portions of the stepped surface, wherein the lower portion of the stepped surface on which the base terminal is formed is situated between an edge of the stepped surface and the upper portions thereof on which the collector and emitter terminals are respectively formed and the lower portion of the stepped surface on which the emitter-base terminal is formed is situated between the upper portions of the stepped surface on which the collector and emitter terminals are respectively formed.