Address control system for segmented buffer memory
First Claim
1. A control system for permitting multiple simultaneous I/O data transfer cycles, in a peripheral controller, to be executed between a host computer which initiates I/O data transfer commands, and multiple numbers (n) of peripheral terminal units, the combination comprising:
- (a) a segmented buffer memory means having "n+1" addressable page segments and "m" addressable word locations in each of the first "n" of said page segments and wherein(i) each one of said addressable page segments, except the "n+1"th segment, is exclusively dedicated to a different one of said "n" peripheral terminal units;
(ii) said "n+1"th segment includes;
(iia) "n" scratch pad areas, addressable by a scratch pad address register, such that one of said "n" scratch pad areas is exclusively dedicated to a different one of said "n" peripheral terminal units and each one of said "n" scratch pad areas functions to hold status information on the status of each I/O instruction initiated by a processor means;
(b) memory address means for addressing page segments and word locations in said segmented buffer memory means, said memory address means including;
(b1) a peripheral address register, controlled by an arithmetic logic unit, for selecting one of said "n+1" page segments and "m" word locations for data being transferred out of said buffer memory means to a selected peripheral terminal unit or for data being transferred from a selected peripheral terminal unit to said buffer memory means;
(b2) a system address register, controlled by said arithmetic logic unit, for selecting one of said "n+1" page segments and "m" word locations for data being transferred from said host computer to said buffer memory means or for data being transferred from said buffer memory means to said host computer;
(b3) said scratch pad address register for addressing only the "n+1" page segment and the "m" word locations therein;
(c) said processor means including an arithmetic logic unit for controlling the execution of data transfers and for controlling said peripheral, system, and scratch pad address registers.
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Accused Products
Abstract
A buffer memory in a peripheral controller has dedicated page and word location segments for each one of a multiple number of attached peripheral units. Additionally, an auxiliary segment provides memory for the active status of each one of the multiple number of data transfer cycle operations which may be occurring concurrently and which status can be accessed at the optimum time so that each initiated data transfer cycle can be completed in a time-saving fashion. Memory address control means are provided for accessing page segments and word locations therein in order to insert data therein or to remove data therefrom. A special queue segment is available to provide concurrent status information for each I/O command initiated by a host computer.
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Citations
13 Claims
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1. A control system for permitting multiple simultaneous I/O data transfer cycles, in a peripheral controller, to be executed between a host computer which initiates I/O data transfer commands, and multiple numbers (n) of peripheral terminal units, the combination comprising:
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(a) a segmented buffer memory means having "n+1" addressable page segments and "m" addressable word locations in each of the first "n" of said page segments and wherein (i) each one of said addressable page segments, except the "n+1"th segment, is exclusively dedicated to a different one of said "n" peripheral terminal units; (ii) said "n+1"th segment includes; (iia) "n" scratch pad areas, addressable by a scratch pad address register, such that one of said "n" scratch pad areas is exclusively dedicated to a different one of said "n" peripheral terminal units and each one of said "n" scratch pad areas functions to hold status information on the status of each I/O instruction initiated by a processor means; (b) memory address means for addressing page segments and word locations in said segmented buffer memory means, said memory address means including; (b1) a peripheral address register, controlled by an arithmetic logic unit, for selecting one of said "n+1" page segments and "m" word locations for data being transferred out of said buffer memory means to a selected peripheral terminal unit or for data being transferred from a selected peripheral terminal unit to said buffer memory means; (b2) a system address register, controlled by said arithmetic logic unit, for selecting one of said "n+1" page segments and "m" word locations for data being transferred from said host computer to said buffer memory means or for data being transferred from said buffer memory means to said host computer; (b3) said scratch pad address register for addressing only the "n+1" page segment and the "m" word locations therein; (c) said processor means including an arithmetic logic unit for controlling the execution of data transfers and for controlling said peripheral, system, and scratch pad address registers. - View Dependent Claims (2, 3, 4, 5)
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6. In a peripheral controller which manages data transfer cycles between a host computer, which initiates data transfer commands, and a plurality of "n" attached peripheral units,
a system for enabling the simultaneous and concurrent execution of a multiple number of I/O data transfer cycles, comprising in combination: -
(a) buffer memory means having a plurality of "n" page-segments such that at least one page-segment is dedicated to each one of said plurality of "n" peripheral units, said buffer memory means including; (a1) an auxiliary "n+1"th page-segment for storing each initiated data transfer command and its status of completion/incompletion, said "n+1"th page-segment including "n" scratch pad areas wherein each scratch pad area is dedicated for holding status information on I/O operations between said host computer and an associated one of said "n" peripheral units; (a2 ) "m" data storage locations in each said page-segment; (b) address means for accessing said page-segments and data storage locations for storage data undergoing transfer into or retrieving data undergoing transfer out of said data storage locations, said address means including; (b1) means for accessing any selected one of said dedicated scratch pad areas in said "n+1"th page-segment; (c) processor means for executing said initiated data transfer commands and including; (c1) arithmetic logic unit means for controlling said address means to enable temporary storage, in said buffer memory means, of data undergoing transfer to/from each of said peripheral units and from/to said host computer. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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Specification