Semiconductor memory device capable of selective operation of memory cell blocks

• US 4,905,201 A
• Filed: 06/05/1987
• Issued: 02/27/1990
• Est. Priority Date: 06/06/1986
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ohira, Tsuyoshi, Nakano, Tomio
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/059,063
• Time in Patent Office: 998 Days
• Field of Search: 365/230, 365/233, 365/189, 365/230.03, 365/230.06, 365/189.08, 365/230.08
• US Class Current: 365/230.03
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor memory device having a memory cell array constituted by a plurality of memory cell blocks includes a clock generator unit constituted by a plurality of clock generator sections, each of the clock generator sections corresponding to each of the memory cell blocks, and a block selector unit for selecting one of the clock generator sections in correspondence with the row address of a designated address. Accordingly, only a clock generator section corresponding to the selected memory cell block is operated by the designated address.

Claims

1. A semiconductor memory device including row decoders and column decoders, comprising:

a memory cell array including a plurality of memory cell blocks, each of said memory cell blocks being respectively operatively connected to one of the row decoders and one of the column decoders;

clock generator means including a plurality of clock generator sections, each of said clock generator sections corresponding to one of said memory cell blocks and each of said clock generator sections sequentially generating a plurality of clock signals for driving corresponding memory cell blocks;

address drive generator means for generating an address drive signal;

address buffer means, coupled to said address drive generator means, for receiving the address drive signal and outputting address bit signals; and

block selector means, coupled to said clock generator means, for selecting one of said clock generator sections in correspondence with the row address of a designated address and causing clock signals of only said selected clock generator section to be output for operating a corresponding one of said memory cell blocks, said block selector means comprising;

a plurality of two-input logic gates having first input terminals for receiving address drive signals from said address drive generator, means, and second input terminals for receiving address bit signals from said address buffer,

whereby only a clock generator section corresponding to said selected memory cell block is operated by said designated address.

2. A semiconductor memory device according to claim 1, further comprising a block selector connected to said clock generator means, wherein each of said clock generator sections receives a signal from said block selector.

3. A semiconductor memory device according to claim 1, further comprising:

word drivers coupled to said respective memory cell blocks; and

circuits including a sense amplifier and an input/output circuit;

wherein each of said clock generator sections comprises series connected buffers operating with predetermined time delays for delivering signals to said respective word drivers and to said respective circuits including said sense amplifier and said input/output circuit.

4. A semiconductor memory device according to claim 1, wherein said plurality of two input logic gates include a plurality of NAND gates.

5. A semiconductor device according to claim 4, wherein said block selector means further comprises a plurality of inverters respectively connected in series with said NAND gates.