Integrated circuit device

• US 4,906,872 A
• Filed: 03/28/1989
• Issued: 03/06/1990
• Est. Priority Date: 03/29/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Shigeru
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Wambach, Margaret Rose
• Application Number:
  US07/329,716
• Time in Patent Office: 343 Days
• Field of Search: 307/480, 307/303, 307/303.1, 364/488-491
• US Class Current: 327/297
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

In an integrataed circuit device such as a logic LSI having a row structure, each row includes a group of logic elements and a clock driver. Each clock driver is connected to a clock signal input wiring, a primary power supply wiring, and a primary ground wiring. The output terminals of the clock drivers in the rows are short-circuited by a clock signal output short-circuiting wiring.

Claims

1. An integrated circuit device comprising:

a primary power supply wiring connected to a power supply;

a primary ground wiring connected to a ground terminal, for holding a reference potential;

primary clock driver means for receiving a clock signal from a clock signal input terminal;

a first clock signal input wiring for connecting said clock signal input terminal to said primary clock driver means;

a first row including a first secondary clock driver having a clock signal input terminal connected to said primary clock driver means through a second clock signal input wiring, a power supply terminal connected to a primary power supply wiring, and a ground terminal connected to a primary ground wiring, and a first group of a plurality of logic elements, which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said primary power supply wiring and said primary ground wiring;

a first secondary power supply wiring for connecting said primary power supply wiring to said power supply terminal of said first secondary clock driver in said first row and to said power supply terminals of said first group of logic elements;

a first secondary ground wiring for connecting said primary ground wiring to said ground terminal of said first secondary clock driver in said first row and to said ground terminals of said logic elements;

a second row arranged parallel to a longitudinal direction of said first row, said second row including a second secondary clock driver having a clock signal input terminal connected to said primary clock driver means through said second clock signal input wiring, a power supply terminal connected to said primary power supply wiring, and a ground terminal connected to said primary ground wiring, and a second group of a plurality of logic elements, which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said primary power supply wiring and said primary ground wiring;

a second secondary power supply wiring for connecting said primary power supply wiring to said power supply terminal of said second secondary clock driver in said second row and to said power supply terminals of said second group of logic elements;

a second secondary ground wiring for connecting said primary ground wiring to said ground terminal of said second secondary clock driver in said second row and to said ground terminals of said logic elements;

a second clock signal input wiring for connecting the input terminals of said first and second secondary clock drivers to an output terminal of said primary clock driver means; and

a clock signal output short-circuiting wiring connected to the clock signal output terminals of said first and second secondary clock drivers.

2. A device according to claim 1, wherein said first secondary clock driver included in said first row, and said second secondary clock driver included in said second row are respectively arranged at one end of said first row and one end of said second row to be adjacent to said primary power supply wiring and said primary ground wiring.

3. A device according to claim 1, wherein said second clock signal input wiring and said clock signal output short-circuiting wiring are arranged on said first secondary clock driver included in said first row, and said second secondary clock driver included in said second row along a direction perpendicular to the longitudinal direction of said drivers.

4. An integrated circuit device comprising:

first and second primary power supply wirings commonly connected to a power supply, and divided to be arranged as two lines;

first and second primary ground wirings commonly connected to a ground terminal, and divided to be arranged as two lines, for holding a reference potential;

primary clock driver means for receiving a clock signal from a clock signal input terminal;

a first clock signal input wiring for connecting said clock signal input terminal to said primary clock driver means;

a first row including first and second secondary clock drivers, said drivers respectively having clock signal input terminals connected to said primary clock driver means through second clock signal input wirings, power supply terminals respectively connected to said first and second primary power supply wirings, and ground terminals respectively connected to said first and second primary ground wirings, and a first group of a plurality of logic elements, which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said first and second primary power supply wirings and said first and second primary ground wirings;

a first secondary power supply wiring for respectively connecting said first and second primary power supply wirings to said power supply terminals of said first and second secondary clock drivers in said first row and to said power supply terminals of said first group of logic elements;

a first secondary ground wiring for respectively connecting said first and second primary ground wirings to said ground terminals of said first and second secondary clock drivers in said first row and to said ground terminals of said first group of logic elements;

a second row arranged parallel in the longitudinal direction of said first row, said second row including first and second secondary clock drivers, said drivers respectively having clock signal input terminals connected to said primary clock driver means through said second clock signal input wirings, power supply terminals connected to said first and second primary power supply wirings, and ground terminals connected to said first and second primary ground wirings, and a second group of a plurality of logic elements, which switch synchronously with the input clock signal, each having a power supply terminal and a ground terminal respectively connected to said first and second primary power supply wirings and said first and second primary ground wirings;

a second secondary power supply wiring for connecting said first and second primary power supply wirings to said power supply terminals of said first and second secondary clock drivers in said second row and to said power supply terminals of said second group of logic elements;

a second secondary ground wiring for connecting said first and second primary ground wirings to said ground terminals of said first and second secondary clock drivers in said second row and to said ground terminals of said second group of logic elements;

a second clock signal input wirings divided from an output terminal of said primary clock driver means, and respectively connected to said first secondary clock drivers and second secondary clock drivers, respectively, included in said first and second rows;

a first output short-circuiting wiring for connecting said first secondary clock drivers in said first row and said second row and a second output short-circuiting wiring for connecting said second secondary clock drivers to each other; and

a clock signal wiring for commonly connecting said first clock signal output short-circuiting wiring to said first and second groups of logic elements corresponding to said first and second rows and included therein, and a second clock signal wiring for commonly connecting said second clock signal output short-circuiting wiring to said first and second groups of logic elements corresponding to said first and second rows and included therein;

a first clock signal wiring for connecting said clock signal output short-circuiting wiring to said first group of logic elements; and

a second clock signal wiring for connecting said clock signal output short-circuiting wiring to said second group of logic elements.

5. A device according to claim 4, wherein said first and second secondary clock drivers included in said first row, and said first and second secondary clock drivers included in said second row are respectively arranged at ends of said first and second rows to be adjacent to said first and second primary power supply wirings and said first and second primary ground wirings.

6. A device according to claim 4, wherein said clock signal input wirings and said clock signal output short-circuiting wirings are respectively arranged on said first and second secondary clock drivers respectively included in said first and second rows along a direction perpendicular to the longitudinal direction of said rows.