Display data memory

• US 4,906,983 A
• Filed: 12/09/1987
• Issued: 03/06/1990
• Est. Priority Date: 08/16/1985
• Status: Expired due to Term

• Current Assignee: BAE Systems Plc
• Original Assignee: British Aerospace, Inc.
• Inventors: Parker, Martin
• Primary Examiner(s): Yusko, Donald J.
• Assistant Examiner(s): Holloway, III, Edwin C.
• Application Number:
  US07/133,251
• Time in Patent Office: 818 Days
• Field of Search: 340/825.79, 340/747, 340/728, 340/750, 340/799, 340/825.83, 340/825.88, 340/718, 340/719, 340/800, 340/801, 364/518, 364/521
• US Class Current: 345/530
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

The device includes a plurality of pixel control digit storage elements (1) each for association with a particular pixel of the display and functionally organized in the form of a two-dimensional array corresponding to the array of pixels of the display, interconnected with one another and with data and control signal input means (2, 3, 4) such that a pixel control digit, representing a given color or intensity say, entered into one "seed" element (i,j) automatically propagates through the device from one to another element until it reaches elements to which boundary indicative control signals are applied by way of said input means when propagation ceases. The boundary indicative control signals and the "seed" element may be derived from and chosen by an associated computer processor operating according to a conventional shape designing algorithm.

Claims

1. A graphic display data memory device for controlling a plurality of pixels of an image, comprising:

a plurality of interconnected modules, each for controlling a pixel, each comprising;

(a) interface means connected to receive input from all adjacent ones of said modules and to provide output to all adjacent ones of said modules, and having a first terminal adapted to receive a control digit thereon and a second terminal adapted to receive a boundary indicative signal thereon; and

(b) latch means, connected to said interface means, for receiving said control digit either;

(a1) from said first terminal, or

(a2) as part of said input from any of said adjacent modules via said interface means,

and responsive to said boundary indicative signal, for, when said boundary indicative signal indicates no boundary;

(b1) producing a signal to control said pixel, and

(b2) producing an output signal of said control digit and passing said output signal to said interface means to be passed to said all adjacent modules, so that said control digit passes to said all adjacent modules when said module is not a boundary module,

and when said boundary indicative signal indicates a boundary, not producing said output signal to thereby prevent said control digit from spreading beyond a boundary defined by modules which are supplied with said boundary signal.

2. A device as in claim 1 wherein each said module is interconnected to four other of said modules to form a two-dimensional array.

3. A device as in claim 1 wherein said control digit comprises a plurality, n of bits, and wherein said interface means comprises said plurality n of multiple input `OR` gates, inputs to one input to each said `OR` gate being connected, respectively, to each said adjacent module to receive said output signal indicative of said control digit therefrom.

4. A device as in claim 3 wherein another input to said multiple input `OR` gates is said input from said first terminal adapted to receive said control digit thereon.

5. A device as in claim 4 wherein said interface means further comprises a plurality of fan-out amplifiers for providing said output signal to said adjacent modules.

6. A device as in claim 5 wherein said latch means is a multi-digit latch, and said boundary indicative signal selectively enables said latch.

7. A graphic display data memory device comprising:

a plurality of interconnected modules, each controlling a pixel (i, j), and each said interconnected module for pixel (i,j) comprising;

(a) interface means, connected to receive input from all adjacent modules which includes a control digit, said adjacent modules including module (i-1, j), module (i+1, j), module (i, j-1) and module (i, j+1) and to provide output to all of said adjacent modules, said interface means further comprising a first terminal adapted to receive said control digit thereon, and a second terminal for receiving a boundary indicative signal thereon, said boundary indicative signal having a boundary state which indicates that said module (i, j) is a boundary module, and a non-boundary state indicating that said module (i, j) is not a boundary module;

(b) a plurality of means for selecting an active control digit, among any of said inputs from said adjacent modules; and

(c) latch gating means, receiving input from said control digit selecting means and from said interface means, for receiving said control digit from either of said first terminal or from said control digit selecting means, and responsive to said boundary indicative signal for;

(a) producing a signal to control said pixel (i, j) when said boundary indicative signal is in said non-boundary state;

(b) producing an output signal indicative of said control digit and passing said output signal to said interface means when said boundary indicative signal is in said non-boundary state, thereby passing said output signal to all of said adjacent modules (i-1, j);

(i+1, j);

(i, j-1);

1;

l );

(i, j+1); and

(c) when said boundary indicative signal indicates a boundary state, not passing said digit to said output.

8. A device as in claim 7 wherein said control digit selecting means is a multiple input `OR` gate.

9. A device as in claim 8 wherein said first terminal is also connected to one input of said multiple input `OR` gate.

10. A device as in claim 9 wherein said interface means comprises a plurality of fan-out amplifiers for amplifying said signal to provide said signal to all of said adjacent modules.

11. A method of controlling the values of a two-dimensional array of connected pixels defining an image area comprising the steps of:

labelling a plurality of pixels in the array and bordering a selected region of the image area with boundary indicative signals;

applying a pixel value control signal to one of the pixels within the region;

subsequently propagating said pixel value control signal to all pixels connected to said one of the pixels and all pixels connected to those and so on to propagate the pixel value control signal to all pixels within the image area except those pixels labelled with boundary indicative signals and beyond;

continuing said propagating until all pixels labelled with boundary indicative signals have been reached; and

setting all pixels to which the pixel value control signal has been propagated and applied to a predetermined regional value, to fill the whole of said selected region of the image area with pixels having said predetermined regional value.