Semiconductor arrangement having at least one semiconductor body

• US 4,907,068 A
• Filed: 12/24/1987
• Issued: 03/06/1990
• Est. Priority Date: 01/21/1987
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Lorenz, Leo, Amann, Heinz
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/137,607
• Time in Patent Office: 803 Days
• Field of Search: 357/68, 357/80, 357/74, 357/75, 357/71, 357/72
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

In a semiconductor arrangement having at least one semiconductor body located on an insulating substrate provided with interconnects, a low-inductance arrangement can be achieved in that the connecting leads are arranged in close proximity to one another and at least partially parallel to one another.

Claims

1. A semiconductor arrangement comprising:

at least first, second, third and fourth parallel electrically separated interconnects arranged on one and the same surface of a substrate;

on the first interconnect a plurality of semiconductor bodies being arranged in a row and each semiconductor body being electrically connected to the first interconnect by a first contact;

each of the semiconductor bodies having a second contact and a third contact, the second contacts being connected by first wires to the second interconnect and by second wires to the third interconnect, the third contacts being connected by third wires to the fourth interconnect, a first connecting lead and a second connecting lead being secured to portions of the first interconnect and the second interconnect, respectively, which lie adjacent to one another and parallel to one another;

the first and second connecting leads located in close proximity, and at least partially parallel to one another, the first and second connecting leads being positioned at a right angle to the substrate surface;

the third interconnect and the fourth interconnect connected to a first terminal and a second terminal, respectively.

2. The semiconductor arrangement according to claim 1, wherein the first and second interconnects of the first, second, third and fourth interconnects are each fashioned mirror-image symmetrical;

wherein the semiconductor bodies are located on the second interconnect with symmetrically distribution; and

wherein the connecting leads are connected to the corresponding interconnects on opposed sides of an axis of symmetry.

3. The semiconductor arrangement according to claim 1, wherein a space between the two connecting leads is filled with a dielectric which has a relative dielectric constant greater than one.

4. The semiconductor arrangement according to claim 3, wherein an insulator foil is arranged between the two connecting leads.

5. A semiconductor arrangement comprising:

an insulating substrate;

at least first, second, third and fourth parallel interconnects arranged on a same surface of the substrate and electrically separated from one another;

a plurality of semiconductor bodies each having at least first, second and third contacts and located in a row on the first interconnect , the second contacts electrically connected to the second interconnect and to the third interconnect, and the third contacts electrically connected to the fourth interconnect, the semiconductor bodies being electrically connected to the first interconnect by the first contact;

at least first and second connecting leads secured to the first and second interconnects, respectively, the connecting leads located in close proximity and at least partially parallel to one another, the two interconnects being parallel to one another and the connecting leads being secured to portions of the interconnects which lie adjacent and parallel to one another, the connecting leads being positioned at substantially a right angle to the surface of the substrate;

the third interconnect and the fourth interconnect connected to a first terminal and a second terminal, respectively.

6. A semiconductor arrangement according to claim 5, wherein the first and second interconnects are configured with mirror-image symmetry about an axis of symmetry on the surface of the substrate, the plurality of semiconductor bodies located on the first interconnect arranged symmetrically thereon about the axis of symmetry, and wherein the first and second connecting leads are connected to the corresponding first and second interconnects on opposed sides of the axis of symmetry.

7. A semiconductor arrangement according to claim 5, wherein a space between the two connecting leads is filled with a dielectric which has a relative dielectric constant greater than one.

8. A semiconductor arrangement according to claim 7, wherein an insulator foil is arranged between the two connecting leads.