Method and apparatus for overlaying a displayable image with a second image

• US 4,907,086 A
• Filed: 09/04/1987
• Issued: 03/06/1990
• Est. Priority Date: 09/04/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Truong, Loc
• Primary Examiner(s): Chin, Tommy P.
• Application Number:
  US07/093,462
• Time in Patent Office: 914 Days
• Field of Search: 358/183, 358/22, 358/185, 358/182, 340/734, 340/791, 340/799
• US Class Current: 348/584
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: H04N 5/272 Means for inserting a foreground image in a background image, i.e. inlay, outlay

Abstract

The overlaying of video image data from an external source, such as a video camera, onto a representation of display data becomes accomplished by using a serial port of an auxiliary frame buffer to receive the serial data from the external source. The source data then becomes transferred from serial registers included within the auxiliary frame buffer into the randomly accessible array of the auxiliary frame buffer. Subsequent execution of a DMA (Direct Memory Access) places the source data overlaid into the image data in the master frame buffer for communication to the video display. Separate designation of the memory address in the auxiliary frame buffer and the main frame buffer allow the overlaying of data from the auxiliary frame buffer into the main frame buffer asynchronously or in a manner not requiring synchronization of the displayed positions relative to one another.

Claims

1. A display system, comprising:

a video display providing a visual display from timed video data;

a first frame buffer, connected to said display, for storing data representative of a primary image to be displayed by said display and supplying said timed video data to said display;

a data source providing timed source data corresponding to an overlay image;

a second frame buffer, connected to said data source, for receiving and storing said source data presented by said data source;

a first addressing circuit, connected to said first frame buffer, for presenting address and control signals thereto;

a second addressing circuit, connected to said second frame buffer, for presenting address and control signals thereto; and

a data bus, connected between said first and second frame buffers, communicating data therebetween free from synchronization with said timed video data and said timed source data, so that the contents of said second frame buffer containing said overlay image is communicated to said first frame buffer for writing thereinto.

2. The system of claim 1, in which said first addressing circuit includes

a destination address register for storing said address signals corresponding to the location in said first frame buffer at which the overlay image is to be stored;

and said second addressing circuit includes

a source address register for storing said address signals corresponding to the location in said second frame buffer containing said overlay image.

3. The system of claim 2, further including a host computer that includes

a host interface, connected to said data bus, for communicating data to and from said data bus, said host computer being external to said system.

4. The system of claim 3, wherein said host interface is connected to said first addressing circuit for providing address information thereto.

5. The system of claim 1, wherein said second frame buffer includes a bank of dual-port random access memories, said dual-port random access memories each including:

a serial input, connected to said data source, for receiving said timed source data therefrom.

6. The system of claim 5, wherein said first frame buffer includes a bank of dual-port random access memories, said dual-port random access memories each including:

a serial output, connected to said video display for presenting said timed video data thereto.

7. The system of claim 1, wherein said data source includes a video camera.

8. A method of overlaying a first displayed image with a second image, said first image being displayed in response to timed video data and said second image being supplied as timed source data, said method comprising:

A. supplying said timed video data for said first displayed image from a first buffer memory having plural addressable locations;

B. placing said timed source data representing said second image in a second buffer memory having plural addressable locations; and

C. moving said source data from selected locations in said second buffer memory to selected locations in said first buffer memory free from the timing of said timed video data and said timed source data.

9. The method of claim 8 in which said placing includes writing said timed source data into a serial port of a video random access memory forming said second buffer memory and said moving includes reading said timed source data from a parallel port of said video random access memory forming said second buffer memory.

10. The method of claim 8 in which said supplying includes reading said timed video data from a serial port of a video random access memory forming said first buffer memory and said moving includes writing said timed source data into a parallel port of said video random access memory forming said first memory.

11. The method of claim 8 in which said moving includes moving a part of said timed source data to part of said locations in said first buffer memory.

12. The method of claim 8 in which said moving includes setting start addresses of selected locations in each of said first and second buffer memories and stepping through sequential addresses to move said timed source data to said first buffer memory.

13. The method of claim 8 including writing host data to said first buffer memory from a host circuit.

14. The method of claim 8 in which said moving includes performing sequential direct memory accesses of said first and second buffer memories.

15. The method of claim 14 in which said performing includes presenting a source address to said second buffer memory in conjunction with a read signal thereto for reading timed source data therein and presenting a destination address to said first buffer in conjunction with a write signal thereto for writing said timed source data therein.