MOS transistor circuit

• US 4,907,201 A
• Filed: 07/14/1988
• Issued: 03/06/1990
• Est. Priority Date: 05/07/1986
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Minami, Hiroshi, Fujita, Koreaki
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/218,888
• Time in Patent Office: 600 Days
• Field of Search: 365/206, 365/207, 365/208, 307/304
• US Class Current: 365/207
• CPC Class Codes: H03F 2203/45364 the AAC comprising multiple transistors parallel coupled at their gates and sources only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 2203/45712 the LC comprising a capacitor as shunt
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together third and fourth MOS transistors respectively connected in series with the first and second transistors, the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuit), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory cells, each of which delivers a complementary pair of bitline signals when accessed;

and at least one sense amplifier connected to receive said bitline signals from an accessed one of said cells;

wherein said sense amplifier comprises first and second voltage amplifiers, each including;

first and second active loads;

first and second drive transistors, connected to pull current through said first and second active loads respectively;

said first drive transistor and active load being connected at a first node, which is also connected to regulate the impedance of said first and second active loads, and said second drive transistor and active load being connected at a second node, which is also connected to provide an output signal of said voltage amplifier;

said first drive transistor of said first voltage amplifier and said second drive transistor of said second voltage amplifier being connected to receive one of said bitline signals, and said first drive transistor of said second voltage amplifier and said second drive transistor of said first voltage amplifier being connected to receive the other one of said bitline signals;

said second node of said first voltage amplifier also being coupled to partially drive said first node of said second voltage amplifier, and said second node of said second voltage amplifier also being coupled to partially drive said first node of said first voltage amplifier.

2. A device as claimed in claim 1, wherein said drive transistors are field effect transistors.

3. A device as claimed in claim 1, wherein said active loads are field effect transistors.

4. A device as claimed in claim 1 wherein said active loads and said drive transistors are field effect transistors.

5. A device as claimed in claim 1 wherein said active loads are P-MOS transistors and said drive transistors are N-MOS transistors.