High voltage power IC process

• US 4,908,328 A
• Filed: 06/06/1989
• Issued: 03/13/1990
• Est. Priority Date: 06/06/1989
• Status: Expired due to Fees

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Hu, Chenming, Sapp, Steven P.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Quach, T. N.
• Application Number:
  US07/361,894
• Time in Patent Office: 280 Days
• Field of Search: 437/40, 437/51, 437/54, 437/62, 437/63, 437/64, 437/66, 437/67, 437/68, 437/77, 437/78, 437/89, 437/90, 437/203, 437/915, 148/DIG. 12, 148/DIG. 26, 148/DIG. 135, 357/55
• US Class Current: 438/269
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 148/026 Deposition thru hole in mask
• CPC Class Codes: Y10S 148/135 Removal of substrate

Abstract

A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.

Claims

1. A process for forming high voltage transistors in a semiconductor wafer which will include low voltage conventional transistors, said process including the steps:

starting with a first wafer of semiconductor material having a resistivity suitable for the fabrication of said low voltage transistors and a second wafer of semiconductor material having a resistivity that is substantially lower than that of said first wafer;

forming at least one epitaxial layer of semiconductor material on one face of said second wafer;

polishing a face of said first wafer and the face of said epitaxial layer of said second wafer to produce flat mirror finishes thereon;

forming an oxide on each wafer on said polished faces;

washing said oxide coated wafer faces to render them hydrophilic;

placing said hydrophilic faces together to produce adhesion between said first and second wafers;

heating said adhered wafers to coalesce said oxide coatings thereby to join said first and second wafers into a unitary structure;

grinding and etching said exposed face of said first wafer until a predetermined thickness thereof remains;

etching a groove in said first wafer that extends through it and through said oxide that joins said wafers together to expose a portion of said epitaxial layer;

backfilling said groove with epitaxially deposited semiconductor material;

shaping the exposed surface of said first wafer for subsequent planar processing; and

forming a high voltage transistor in said backfilled semiconductor material.

2. The process of claim 1, wherein said step of forming at least one epitaxial layer includes the deposition of a plurality of epitaxial layers.

3. The process of claim 1 wherein said grinding and etching step removes a major portion of said first wafer.

4. The process of claim 3 wherein the remaining thickness of said first wafer is on the order of a few microns.

5. The process of claim 1 wherein said first wafer is provided with a high conductivity face by doping the face to be oxidized prior to oxidation.

6. The process of claim 5 wherein said doping involves a slow diffusing impurity having the same doping conductivity type as that of said first wafer.

7. The process of claim 1 wherein said step of forming a high voltage transistor includes the steps:

diffusing an impurity into said backfilled material having an opposite conductivity characteristic to a first depth that is less than the final thickness of said first wafer to create a transistor base region;

diffusing an impurity having the same conductivity characteristic as said backfilled material into said base region within the confines thereof and to a lesser depth to create a transistor emitter region; and

providing contacts to said base and emitter regions and a contact to said second wafer to form a collector contact.

8. The process of claim 1 wherein said step of forming a high voltage transistor includes the steps:

diffusing an impurity having an opposite conductivity type into said backfilled material to a first depth that is less than the final thickness of said first wafer to create a transistor channel region;

diffusing an impurity having the same conductivity type as said backfilled material into said channel region within the confines thereof and to a lesser depth to create a a transistor source region;

forming a gate oxide that overlaps the channel region that exists between the edge of channel diffusion and the source diffusion;

forming a gate conductor over said gate oxide thereby to provide a transistor gate;

forming a metal contact to both said source and said channel regions outside the confines of said gate whereby said source is contacted and shorted to said channel thereby to form a transistor source combined with a transistor back gate contact; and

forming a contact to said second wafer thereby to provide a transistor drain electrode.