Switched capacitor sampling filter

• US 4,908,579 A
• Filed: 08/24/1988
• Issued: 03/13/1990
• Est. Priority Date: 08/26/1987
• Status: Expired due to Fees

• Current Assignee: L'Etat Francais Represente PAR Le Ministre Des Postes et Telecommunications
• Original Assignee: L'Etat Francais Represente PAR Le Ministre Des Postes et Telecommunications
• Inventors: Tawfik, Mohamed S., Senn, Patrice
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/235,495
• Time in Patent Office: 566 Days
• Field of Search: 307/520, 307/521, 328/167, 328/151, 330/107, 330/109, 330/9, 333/173
• US Class Current: 327/554
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

This filter circuit comprises at least one basic cell (2) arranged as a switched capacitor sampling filter, together with a clock suitable for defining two different states for controlling sampling. According to the main characteristic of the invention, the circuit includes upstream switching means (4) suitable for inverting the polarity of the signal input to the cell during one of the two states, and downstream switching means (6) suitable for inverting the output signal from the cell (2). This makes it possible to transpose the filtering frequency band of the cell (2). The circuit is applicable to manufacturing switched capacitor sampling filters in the form of integrated circuits.

Claims

1. A circuit of the type comprising at least one basic cell arranged as a switched capacitor low pass sampling filter, together with a clock suitable for defining two different states for controlling sampling, wherein the circuit further comprises:

upstream switching means suitable for inverting the polarity of an input signal to the cell during one of the two states; and

downstream switching means suitable for inverting an output signal from the cell, thereby making it possible to transpose the filtering frequency band of the cell from low-pass to high pass.

2. A circuit according to claim 1 wherein the basic cell comprises:

a first differential amplifier whose negative input is connected via a first capacitor to the output of said first amplifier which delivers the output signal from the cell and whose positive input is grounded;

a first switch connected to one of the plates of a second capacitor, said first switch being suitable, under the control of the clock for establishing an electrical connection between said second capacitor and the negative input of the first amplifier or between said second capacitor and ground; and

a second switch connected to the other plate of the second capacitor, said second switch being suitable, under the control of the clock, for establishing an electrical connection between said second capacitor and a positive terminal of the basic cell or between said second capacitor and a negative terminal of the cell which receives the input signal of the cell.

3. A circuit according to claim 1, wherein the upstream switching means comprise:

a third switch connected to a positive terminal of the basic cell, said third switch being suitable, under the control of the clock, for establishing an electrical connection between said positive terminal and ground or between said positive terminal and the input signal; and

a fourth switch connected to a negative terminal of the basic cell, said fourth switch being suitable, under the control of the clock, for establishing an electrical connection between said negative terminal and ground or between said negative terminal and the input signal.

4. A device according to claim 1, wherein the downstream switching means comprise:

a second differential amplifier of the inverting type and suitable, under the control of the clock, for inverting the polarity of the output signal from the circuit as a whole during the other one of the two states;

a fifth switch connected to the output from a first differential amplifier of the cell, said fifth switch being suitable, under the control of the clock, for establishing an electrical connection between the output from the first differential amplifier and a first node or between said output from the first differential amplifier and the input to the second differential amplifier; and

a sixth switch connected to the output of the circuit as a whole, said sixth switch being suitable, under the control of the clock, for establishing an electrical connection between said output from the circuit as a whole and the output of the second differential amplifier or between said output of the circuit as a whole and the first node.

5. A circuit according to claim 1, wherein the downstream switching means are arranged as a sample-and-hold stage, the stage comprising an eighth switch connected to the output from the basic cell via a seventh switch suitable for controllably establishing an electrical connection between the output from the cell and the eighth switch, said eighth switch being suitable, under the control of the clock, for establishing an electrical connection between said seventh switch and the negative input of a third differential amplifier or between said seventh switch and the positive input of said third differential amplifier, the output signal from the circuit as a whole being obtained from the output of the third differential amplifier.

6. A circuit according to claim 1, wherein the basic cell is a double sampling cell.

7. A circuit according to claim 6, wherein the upstream switching means are arranged as a sample-and-hold stage.

8. A circuit according to claim 1, wherein the downstream switching means comprise:

a ninth switch connected to the output from the basic cell, said ninth switch being suitable, under the control of the clock, for establishing an electrical connection between said output from the cell and a second node or between said output from the cell and a third node;

a tenth switch connected to the positive input of a fourth differential amplifier, said tenth switch being suitable, under the control of the clock, for establishing an electrical connection between said positive input and ground or between said positive input and the second node;

a third capacitor connected between the third node and the negative input to the fourth operational amplifier, said third capacitor having an eleventh switch connected in parallel therewith and suitable, under the control of the clock, for establishing an electrical connection between the two plates of said third capacitor; and

a fourth capacitor connected between the negative input of the fourth operational amplifier and the output from said fourth amplifier which delivers the output signal from the circuit as a whole, said fourth capacitor having a twelfth switch connected in parallel therewith and suitable, under the control of the clock, for establishing an electrical connection between the two plates of the fourth capacitor.

9. A circuit according to claim 1, wherein the downstream switching means comprise:

a thirteenth switch connected to the output from the cell, said thirteenth switch being suitable, under the control of the clock, for establishing an electrical connection between said output from the cell and a fourth node;

a fourteenth switch connected to the fourth node, said fourteenth switch being suitable, under the control of the clock, for establishing an electrical connection between said fourth node and a fifth node or between said fourth node and a sixth node;

a fifteenth switch connected to the positive input of a fifth differential amplifier, said fifteenth switch being suitable, under the control of the clock, for establishing an electrical connection between said positive input and ground or between said positive input and the fifth node;

a fifth capacitor connected between the sixth node an the negative input to the fifth operational amplifier, said fifth capacitor having a sixteenth switch connected in parallel therewith and suitable, under the control of the clock, for establishing an electrical connection between the two plates of the fifth capacitor;

a sixth capacitor connected between the negative input of the fifth operational amplifier and the output from said fifth amplifier which delivers the output signal of the circuit as a whole, said sixth capacitor having a seventeenth switch connected in parallel therewith and suitable, under the control of the clock, for establishing an electrical connection between the two plates of the sixth capacitor;

a seventh capacitor having one plate connected to the sixth node and having its other plate connected to ground; and

an eighth capacitor having one plate connected to the positive input of the fifth differential amplifier and whose other plate is connected to ground.