Power MOSFET having a current sensing element of high accuracy

• US 4,908,682 A
• Filed: 04/17/1989
• Issued: 03/13/1990
• Est. Priority Date: 04/19/1988
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Takahashi, Mitsuasa
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US07/339,486
• Time in Patent Office: 330 Days
• Field of Search: 357/23.4, 357/23.14, 357/41, 357/46
• US Class Current: 257/336
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

Herein disclosed is a vertical power MOSFET having a current sensing MOSFET, in which the base region of the current sensing MOSFET is electrically connected with the base region of the vertical MOSFET whereas the current leading-out electrode of the current sensing MOSFET is connected with only the source region of the current sensing MOSFET.

Claims

1. A MOS field effect transistor comprising:

a drain region of one conductivity type;

a plurality of first base regions of the opposite conductivity type formed in one principal surface of said drain region;

a plurality of first source regions of said one conductivity type formed in said first base regions;

a first gate electrode formed over first portions of said first base regions, said first portions being sandwiched between said first source regions and said drain region;

a source electrode connected commonly with said plurality of first base regions and said plurality of first source regions;

a second base region of said opposite conductivity type formed in said one principal surface of said drain region;

a second source region of said one conductivity type formed in said second base region;

a second gate electrode formed over a second portion of said second base region, said second portion being sandwiched between said second source region and said drain region, said second gate electrode being electrically connected with said first gate electrode;

a base electrode electrically connected with said second base region and said first source electrode, said base electrode being not connected with said second source region;

a current leading-out electrode electrically connected with said second source region, said current leading-out electrode being not connected with said second base region; and

a drain electrode electrically connected with said drain region.

2. A MOS field effect transistor as claimed in claim 1, wherein said MOS field effect transistor is of vertical type, in which said drain electrode is formed on the other principal surface opposite to said one principal surface of said drain region.

3. A MOS field effect transistor as claimed in claim 2, wherein said second base region is surrounded by said plurality of first base regions.

4. A vertical MOSFET comprising:

a semiconductor substrate acting as a drain;

a first vertical MOSFET formed in said semiconductor substrate and having a plurality of first base regions and a plurality of first source regions in one principal surface of said semiconductor substrate;

a second vertical MOSFET for current sensing formed in said semiconductor substrate and having a second base region and a second source region in said one principal surface of said semiconductor substrate, said second base region being electrically connected with said first base regions, said second vertical MOSFET further having a current leading-out electrode electrically connected with said second source region, said current leading-out electrode being not connected with said second base region;

a gate electrode formed in said principal surface of said semiconductor substrate so that it may be used commonly for said first vertical MOSFET and said second vertical MOSFET;

a source electrode electrically connected commonly with said plurality of said first base regions and said plurality of said first source regions; and

a drain electrode formed in the other principal surface opposite to said one principal plane of said semiconductor substrate.

5. A vertical MOSFET as claimed in claim 4, wherein said second vertical MOSFET is formed at the center of said first vertical MOSFET.

6. A vertical MOSFET as claimed in claim 5, further comprising:

a first connection pad electrically connected with said second base region ad formed at the center of said semiconductor substrate; and

a second connection pad electrically connected with said current leading-out electrode and formed at the center of said semiconductor substrate.