Anti-aliasing raster operations utilizing sub-pixel crossing information to control pixel shading

• US 4,908,780 A
• Filed: 10/14/1988
• Issued: 03/13/1990
• Est. Priority Date: 10/14/1988
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Priem, Curtis, Malachowsky, Chris, Webber, Thomas
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Bayerl, Raymond J.
• Application Number:
  US07/258,133
• Time in Patent Office: 515 Days
• Field of Search: 364/723, 364/518, 364/521, 340/747, 340/744, 340/723, 340/724, 340/728
• US Class Current: 345/611
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A method and apparatus for performing anti-aliasing of rendered lines, text and images displayed by a workstation on a video display. The anti-aliasing is performed by logically dividing each addressable frame buffer pixel into sixteen sub-pixels and generating a gray scale value for the displayed pixel that is a function of the number of sub-pixels crossed by a portion of a rendered image. The invented circuitry is part of the circuitry used for combining source and destination data which forms the displayed image namely, an anti-aliasing mask and filter, adder/subtractor logic, saturation logic and anti-aliasing logic.

Claims

1. An apparatus including a central processing unit for generating control signals including background color control signals and foreground color control signals, said apparatus for performing Boolean raster operations on source and destination data for storage in a frame buffer memory for a plurality of planes, said source data being selected from one of a font register and a pattern register, said destination data being selected from said frame buffer, wherein said destination data stored in said frame buffer is organized as pixels of information to be displayed, and each of said pixels is logically divided into a plurality of sub-pixels, said apparatus comprising:

(a) source data select means coupled to said font register and said pattern register for selecting source data;

(b) anti-aliasing mask logic coupled to said source data select means and said central processing unit for generating for each of said pixels to be displayed a fraction between 0 and 1 representing the ratio of the number of sub-pixels crossed by an image segment going through the pixel to the total number of sub-pixels within the pixel to the total number of sub-pixels with the pixel corresponding to said sub-pixels;

(c) filter means coupled to said mask logic means for encoding the output generated by said mask logic means, said encoded output corresponding to one of a plurality of shades of gray for each of said pixels to be displayed;

(d) multiplexer means coupled to said central processing unit and said anti-aliasing mask logic means for selecting a Boolean raster operation to be performed for each of said plurality of planes using said foreground color control signals and said background color control signals;

(e) logic means coupled to said multiplexer means and said central processing unit for generating SSEL0 and SSEL1 control signals used by said anti-aliasing mask logic means, a saturation control signal and a +/- control signal;

(f) adder/subracter means coupled to said source data select menas, said frame buffer and said logic means for adding and subtracting the sub-pixel values for each row of sub-pixel information in each pixel;

(g) saturation logic means coupled to said adder/subtracter means for saturating the values output by said adder/subtracter means to values between 0 and 128.

2. The apparatus defined by claim 1 wherein said source data select means comprises a multiplexer for selecting source data form one of said font register and said pattern register under control of said central processing unit.

3. The apparatus defined by claim 1 wherein said anti-aliasing mask logic means comprises:

(a) a plurality of groups of multiplexers, the number of groups of multiplexers corresponding to the number of pixels of information available from said source data select means and whose control inputs are for each of said multiplexers, the source data values of a horizontal row of sub-pixels, a first data input of each of said multiplexers being the signal SSEL0 and a second data input of each of said multiplexers being the signal SSEL1;

(b) a plurality of AND gates, the output of each of said multiplexers being a first input to a corresponding one said plurality of AND gates, a second input of said plurality of AND gates being a signal AAMASK for masking sub-pixel values outputted by a corresponding one of said plurality of multiplexers.

4. The apparatus defined by claim 3 wherein said filter means comprises logic circuitry which sums the outputs of said AND gates and multiplies the number by eight to obtain an eight bit value of 0, 8, 16, 24 or 32.

5. The apparatus defined by claim 1 wherein said multiplexer means comprises a multiplexer whose control inputs are said foreground and background color control signals and whose data input is a number corresponding to said Boolean raster operation to be performed.

6. The apparatus defined by claim 1 wherein said logic means comprises a logic circuit for implementing the following truth tables for the Boolean raster operations CLEAR, ERASE, INVERT, XOR, AND, EQUIVALENT, NOP, PAINT INVERTED, PAINT, and SET having hexidecimal codes of 0, 2, 5, 6, 8, 9, A, B, E and F respectively, and wherein the signals SAT, +/-, SSEL0 and SSEL1 are generated as a function of the Boolean raster operation and a signal PLOT/UNPLOT, where PLOT/UNPLOT=0 means plot and PLOT/UNPLOT=1 means unplot:

space="preserve" listing-type="tabular">______________________________________ RASTER PLOT/ OPERATION UNPLOT SAT +/- SSEL0 SSEL1 ______________________________________ 0 0 1 0 1 1 0 1 1 0 1 1 2 0 1 0 1 0 2 1 1 0 1 0 5 0 0 1 1 1 5 1 0 0 1 1 6 0 0 1 1 0 6 1 0 0 1 0 8 0 1 0 0 1 8 1 1 0 0 1 9 0 0 1 0 1 9 1 0 0 0 1 A 0 0 1 1 0 A 1 0 1 1 0 B 0 1 1 0 1 B 1 1 1 0 1 E 0 1 1 1 0 E 1 1 1 1 0 F 0 1 1 1 1 F 1 1 1 1 1 ______________________________________

7. The apparatus defined by claim 1 wherein said adder/substracter means comprises:

(a) a plurality of exclusive OR gates having one input coupled to a corresponding source data line;

(b) a plurality of full bit adders corresponding to said plurality of exclusive OR gates, the output of each of said plurality of exclusive OR gates coupled to a first input of a corresponding full bit adder, a second input of each of said full bit adders being a corresponding destination data line, there being one destination data line for each bit of said destination data wherein the highest order destination data bit has a high order destination data line;

(c) an AND gate having a first input coupled to said high order destination data line, a second input of said AND gate being said saturation signal;

(d) an exclusive OR gate having a first input coupled to the output of said AND gate, a second input of said exclusive OR gate being said +/- control signal, the output of said exclusive OR gate coupled to a second input of each of said plurality of exclusive OR gates and a carry input of on of said full bit adders.

8. The apparatus defined by claim 7 wherein said saturation logic means comprises:

(a) first and second exclusive OR gates, said first exclusive OR gate having a first input coupled to said first input of said AND gate and a second input coupled to the output of the full bit adder whose second input is said high order destination data line, said second exclusive OR gate having a first input coupled to said second input of said first exclusive OR gate and a second input coupled to sad high order destination data line;

(b) a NAND gate having a first input coupled to said saturation control signal and a second input coupled to the output of said first exclusive OR gate;

(c) a plurality of AND gates having a first input coupled to the output of a corresponding one of said full bit adders excepting for said full bit adder coupled to said high order destination data line, a second input of each of said plurality of AND gates being the output of said NAND gate;

(d) a multiplexer having a first data input coupled to the output of said second exclusive OR gate and a second data input coupled to the output of said full bit adder coupled to said high order destination data line, the control input of said multiplexer being the output of said NAND gate.

9. A method for performing Boolean raster operations on source and destination data for storage in a frame buffer memory for a plurality of planes in a workstation including a central processing unit for generating control signals including background color control signals and foreground color control signals, said source data being selected from one of a font register and a pattern register, said destination data being selected from said frame buffer, wherein said destination data stored in said frame buffer is organized as poxels of information to be displayed, and each of said pixels is logically divided into a plurality of sub-pixels, said method comprising the steps of:

(a) selecting source data from one of said font register and said pattern register;

(b) generating a number corresponding to a gray scale value for each of said pixels to be displayed as a function of the ratio of the number of sub-pixels crossed by an image segment going through the pixel corresponding to said sub-pixels to the total number of sub-pixels within said pixel;

(c) encoding the output generated by said generating step, said encoded putput corresponding to one of a plurality of shades of gray for each of said pixels to be displayed;

(d) selecting a Boolean raster operation to be performed for each of said plurality of planes using said foreground color control signals and said background color control signals;

(e) generating SSEL0 and SSEL1 control signals used by said gray scale value generating step, a saturation control signal and a +/- control signal;

(f) adding and subtracting the sub-pixel values generated by said gray scale value generating step for each row of sub-pixel information in each pixel;

(g) saturating the values output generatied by said adder/subtracter step to values between 0 and 128.

10. The method defined by claim 9 wherein said selecting step comprises the step of selecting source data from one of said font register and said pattern register under control of said central processing unit.

11. The method defined by claim 9 wherein said gray scale value generating step comprises the steps of:

(a) inputting to a plurality of groups of multiplexers, the number of groups of multiplexers corresponding to the number of pixels of information available from said source data select select step as control inputs for each of said multiplexers, the source data values of a horizontal row of sub-pixels, a first data input of each of said multiplexers being the signal SSEL0 and a second data input of each of said multiplexers being the signal SSEL1;

(b) inputting as a first input to a plurality of AND gates, the output of a corresponding one of said multiplexers, a second input of said plurality of AND gates being a signal AAMASK for masking sub-pixel values outputted by a corresponding one of said plurality of multiplexers.

12. The method defined by claim 11 wherein said encoding step sums the outputs of said AND gates and multiplies the number by eight to obtain an eight bit value of 0, 8, 16, 24 or 32.

13. The method defined by claim 9 wherein said Boolean raster operation selection step comprises the steps of inputting to a multiplexer as its control inputs, said foreground and background color control signals, and inputting as the data input of said multiplexer a number corresponding to said Boolean raster operation to be performed.

14. The method defined by claim 9 wherein said adding and subtracting step comprises the steps of:

(a) inputting as one input of a plurality of exclusive OR gates a corresponding source data line;

(b) inputting as a first input to a plurality of full bit adders corresponding to said plurality of exclusive OR gates, the output of each of said plurality of exclusive OR gates, a second input of each of said full bit adders being a corresponding destination data line, there being one destination data line for each bit of said destination data wherein the highest order destination data bit has a high order destination data line;

(c) inputting as a first input to an AND gate said high order destination data line, a second input of said AND gate being said saturation signal;

(d) inputting to an exclusive OR gate the output of said AND gate, a second input of said exclusive OR gate being said +/- control signal, the output of said exclusive OR gate coupled to a second input of each of said plurality of exclusive OR gates and a carry input of one of said full bit adders.

15. The method defined by claim 14 wherein said saturating step comprises the steps of:

(a) inputting as a first input to a first exclusive OR gate, said first input of said AND gate and a second input coupled to the output of the full bit adder whose second input is said high order destination data line, and inputting as a first input of a second exclusive OR gate said second input of said first exclusive OR gate and inputting as a second input of said second exclusive OR gate said high order destination data line;

(b) inputting as a first input to a NAND gate said saturation control signal and as a second input to said NAND gate the output of said first exclusive OR gate;

(c) inputting as a first input to each of a plurality of AND gates the output of a corresponding one of said full bit adders excepting for said full bit adder coupled to said high order destination data line, a second input of each of said plurality of AND gates being the output of said NAND gate;

(d) inputting as a first data input to a multiplexer the output of said second exclusive OR gate and inputting as a second data input to said multiplexer the output of said full bit adder coupled to said high order destination data line, the control input of said multiplexer being the output of said NAND gate.