Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range
First Claim
1. A memory sub-system for an information handling system for automatically creating a linear address range from a plurality of memory arrays installed in a plurality of simultaneously addressable memory banks, regardless of the number and type of said installed arrays, where each different said type of installed array has a different maximum number of addressable storage locations where each said maximum number is an even multiple of the smallest said maximum number, said range comprising a plurality of contiguous segments each of which comprises the same predetermined number of addressable locations, the maximum permissible number of said contiguous segments in said linear address range being a function of the number of said banks and the ratio of address capacities of the arrays having the largest and smallest capacity, said information handling system having a data bus comprising a pre-established number D of data lines and a memory address bus having a total number (H+L) of address lines for addressing said address range, said sub-system comprising,a plurality of said memory banks each of which is addressed simultaneously by a number L of low order memory bus address lines, said number L being determined by the array type having the largest said maximum number of said addressable storage locations of any said array types that are supported by said sub-system,means for developing at each said bank, size signals to indicate the type of array that is installed in said bank,means for generating from selected high order address bus lines a plurality of segment identifying signals corresponding in number to at least said maximum permissible number of said contiguous segments, andlogic means including a plurality of interrelated logic cells each of which includes a plurality of logic elements interrelated in a predetermined combinatorial circuit for assigning said addressable locations of the array installed in each said bank to contiguous said segments of said linear range in response to said segment identifying signals supplied to said logic cells and in accordance with said array size signals for said installed arrays.
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Abstract
A method and system for addressing memory of an information handling system in which the memory comprises a plurality of memory banks, each of which can support a plurality of different predetermined size memory modules. The sizes of the different modules are multiples of the module having the smallest size. In the embodiment described, two different sizes are employed, a 256K capacity module and a 1 Meg. capacity module, either of which can be installed in 1 of 4 memory banks. The maximum addressable address range is therefore 4 Meg. while the minimum memory is 256K. The address range can be increased in increments of 256K corresponding to 1 segment to a total of 16 contiguous segments or 4 Meg. A memory address bus comprising 22 lines is employed in the system. The 20 low order lines address each bank simultaneously. A converter converts the 4 high order address bits 22-19 to 16 sequentially ordered segment lines. A matrix of similar logic cells consisting of combinatorial logic processes each segment line to develop memory bank select signals in accordance with size signals obtained from the modules and supplied to the cells in the first row of the matrix which then provide modified size signals to remaining cells in the respective columns of the matrix. Contiguous address segments are provided from the minimum to the maximum range for every possible combination of memory modules installable in the four banks.
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Citations
11 Claims
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1. A memory sub-system for an information handling system for automatically creating a linear address range from a plurality of memory arrays installed in a plurality of simultaneously addressable memory banks, regardless of the number and type of said installed arrays, where each different said type of installed array has a different maximum number of addressable storage locations where each said maximum number is an even multiple of the smallest said maximum number, said range comprising a plurality of contiguous segments each of which comprises the same predetermined number of addressable locations, the maximum permissible number of said contiguous segments in said linear address range being a function of the number of said banks and the ratio of address capacities of the arrays having the largest and smallest capacity, said information handling system having a data bus comprising a pre-established number D of data lines and a memory address bus having a total number (H+L) of address lines for addressing said address range, said sub-system comprising,
a plurality of said memory banks each of which is addressed simultaneously by a number L of low order memory bus address lines, said number L being determined by the array type having the largest said maximum number of said addressable storage locations of any said array types that are supported by said sub-system, means for developing at each said bank, size signals to indicate the type of array that is installed in said bank, means for generating from selected high order address bus lines a plurality of segment identifying signals corresponding in number to at least said maximum permissible number of said contiguous segments, and logic means including a plurality of interrelated logic cells each of which includes a plurality of logic elements interrelated in a predetermined combinatorial circuit for assigning said addressable locations of the array installed in each said bank to contiguous said segments of said linear range in response to said segment identifying signals supplied to said logic cells and in accordance with said array size signals for said installed arrays.
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10. A method for use in a memory sub-system having a plurality of ordered memory banks for automatically assigning a plurality of memory arrays installed in said banks to an address range of an information handling system, said arrays having different address capacities, said range having a maximum permissible number of contiguous address segments determined by the number of said banks and the ratio of address capacities of the arrays having the largest and smallest capacity, each said segment having a plurality of addressable locations corresponding to the number of addressable locations in said array having said smallest capacity, said banks being addressed concurrently during a memory addressing operation by a plurality of low order memory bus address lines sufficient to generate the number of memory addresses corresponding to the number of address locations in the array having the greatest address capacity which is supported by said sub-system, said method comprising the steps of,
(A) determining said ratio of the address capacities of the array with the largest capacity and the array with the smallest capacity, (B) developing at each said bank, a size signal indicating the address capacity of said array installed in said bank, (C) converting high order address bus signals to a plurality of sequentially ordered segment identifying signals during a memory addressing operation, the number of which is determined by the number of said banks and said ratio, and (D) processing with predetermined combinatorial logic cells, said segment identifying signals in sequential order with said size signals from said plurality of ordered banks during said memory addressing operation to select one of said banks which causes the address location in said array installed in said selected bank to be addressed by said low order memory bus lines regardless of the placement of said arrays relative to said ordered banks.
Specification