Method and apparatus for decoding multiple bit sequences that are transmitted simultaneously in a single channel
First Claim
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1. A method of decoding superimposed data bits including the steps of:
- receiving a composite signal that is formed by coding multiple bit sequences with respective spreading codes and transmitting the coded bit sequences simultaneously and asynchronously over a single channel;
comparing the content of several registers, each of which contains an estimate of a particular bit sequence in said composite signal and a metric for that sequence, to determine the largest metric Mmax and the corresponding bit sequence bs ;
evaluating a new pair of metrics for the very next bit b(x) in said composite signal which follows said bit sequence bs by using estimated "0" and "1" values for bit b(x), bits from said sequence bs which immediately precede bit b(x), and matched filter outputs for bits in said composite signal which immediately follow bit b(x);
replacing the register which contains said bit sequence bs with two registers, one of which contains the bit sequence bs b(x)=0 and the metric Mmax plus the above evaluated metric for b(x)=0, and the other of which contains the bit sequence bs b(x)=1 and the metric Mmax plus the above evaluated metric for b(x)=1;
repeating said comparing, evaluating, and replacing steps multiple times; and
thereafter,decoding said composite signal as the bit sequence in the register which contains the largest metric.
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Abstract
Data bits are decoded from a composite signal that is formed by coding multiple bit sequences with respective spreading codes, and transmitting the coded bit sequences simultaneously and asynchronously over a single channel in which the bit sequences are added. This decoding involves a metric in combination with a repetitive decision process which is only linearly dependent on the number of bit sequences in the composite signal.
195 Citations
10 Claims
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1. A method of decoding superimposed data bits including the steps of:
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receiving a composite signal that is formed by coding multiple bit sequences with respective spreading codes and transmitting the coded bit sequences simultaneously and asynchronously over a single channel; comparing the content of several registers, each of which contains an estimate of a particular bit sequence in said composite signal and a metric for that sequence, to determine the largest metric Mmax and the corresponding bit sequence bs ; evaluating a new pair of metrics for the very next bit b(x) in said composite signal which follows said bit sequence bs by using estimated "0" and "1" values for bit b(x), bits from said sequence bs which immediately precede bit b(x), and matched filter outputs for bits in said composite signal which immediately follow bit b(x); replacing the register which contains said bit sequence bs with two registers, one of which contains the bit sequence bs b(x)=0 and the metric Mmax plus the above evaluated metric for b(x)=0, and the other of which contains the bit sequence bs b(x)=1 and the metric Mmax plus the above evaluated metric for b(x)=1; repeating said comparing, evaluating, and replacing steps multiple times; and
thereafter,decoding said composite signal as the bit sequence in the register which contains the largest metric. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A decoder for decoding superimposed data bits comprising:
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a plurality of filters, which are coupled to receive and filter a composite signal that is formed by coding multiple bit sequences with respective spreading codes and transmitting the coded bit sequences simultaneously and asynchronously over a single channel, with each filter being matched to a respective one of said spreading codes; a computing means for evaluating a metric for any bit b(x) in said composite signal which includes an estimated value for bit b(x), an estimate of a sequence of bits bs which immediately precede bit b(x), and matched filter outputs for several bits in said composite signal which immediately follow bit b(x); a plurality of register means, each of which is for holding a respective metric and a corresponding bit sequence; and a control means for repeatedly (a) examining said registers to determine its largest metric Mmax and corresponding bit sequence bs, (b) directing said computing means to compute a new pair of metrics for the bit sequences bs b(x)=0 and bs b(x)=1, and (c) replacing the register which contains said bit sequence bs with two registers, one of which contains the bit sequence bs b(x)=0 and the metric Mmax plus the above evaluated metric for b(x)=0, and the other of which contains the bit sequence bs b(x)=1 and the metric Mmax plus the above evaluated metric for b(x)=1. - View Dependent Claims (9, 10)
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Specification